top.tan.qmsg

一个圣诞彩灯控制芯片的vrilog源代码

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "test " "Info: Assuming node \"test\" is an undefined clock" {  } { { "top.v" "" { Text "D:/colorlight/light_success/simple8/top.v" 39 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "test" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "osc " "Info: Assuming node \"osc\" is an undefined clock" {  } { { "top.v" "" { Text "D:/colorlight/light_success/simple8/top.v" 39 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "osc" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "zc " "Info: Assuming node \"zc\" is an undefined clock" {  } { { "top.v" "" { Text "D:/colorlight/light_success/simple8/top.v" 39 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "zc" } } } }  } 0}  } {  } 0}