top.fit.qmsg

来自「一个圣诞彩灯控制芯片的vrilog源代码」· QMSG 代码 · 共 22 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 17 10:07:32 2005 " "Info: Processing started: Thu Nov 17 10:07:32 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off colorlight -c top " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off colorlight -c top" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "top EP20K200EFC484-2X " "Info: Selected device EP20K200EFC484-2X for design \"top\"" {  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "sysclk:u0\|clk_4 automatically " "Info: Promoted cell \"sysclk:u0\|clk_4\" to global signal automatically" {  } {  } 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "sysclk:u0\|flag2\[0\] automatically " "Info: Promoted cell \"sysclk:u0\|flag2\[0\]\" to global signal automatically" {  } {  } 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "sysclk_250k:u23\|clk_250k automatically " "Info: Promoted cell \"sysclk_250k:u23\|clk_250k\" to global signal automatically" {  } {  } 0}
{ "Info" "IFIT_FIT_GLOBAL_SIGNAL_PROMOTION" "sysclk:u0\|clk_8 automatically " "Info: Promoted cell \"sysclk:u0\|clk_8\" to global signal automatically" {  } {  } 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "en " "Warning: Node \"en\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "en" } } } }  } 0}  } {  } 0}
{ "Info" "IFIT_FIT_ATTEMPT" "1 Thu Nov 17 2005 10:07:37 " "Info: Started fitting attempt 1 on Thu Nov 17 2005 at 10:07:37" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACER_ESTIMATED_ROUTING_RESOURCE_USAGE" "" "Info: Design requires the following device routing resources:" { { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_COL_FSTTRK" "1 " "Info: Overall column FastTrack interconnect = 1%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_ROW_FSTTRK" "1 " "Info: Overall row FastTrack interconnect = 1%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_COL_FSTTRK" "4 " "Info: Maximum column FastTrack interconnect = 4%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_ROW_FSTTRK" "4 " "Info: Maximum row FastTrack interconnect = 4%" {  } {  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "9.787 ns register register " "Info: Estimated most critical path is register to register delay of 9.787 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.209 ns) 0.209 ns TG:u17\|ein\[0\] 1 REG LAB_6_S2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.209 ns) = 0.209 ns; Loc. = LAB_6_S2; Fanout = 11; REG Node = 'TG:u17\|ein\[0\]'" {  } { { "D:/colorlight/light_success/simple8/db/top_cmp.qrpt" "" { Report "D:/colorlight/light_success/simple8/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/colorlight/light_success/simple8/db/colorlight.quartus_db" { Floorplan "D:/colorlight/light_success/simple8/" "" "" { TG:u17|ein[0] } "NODE_NAME" } "" } } { "TG.v" "" { Text "D:/colorlight/light_success/simple8/TG.v" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.220 ns) + CELL(1.154 ns) 4.583 ns model1_top:u8\|model1:u6\|l1\[0\]~314 2 COMB LAB_12_L2 3 " "Info: 2: + IC(3.220 ns) + CELL(1.154 ns) = 4.583 ns; Loc. = LAB_12_L2; Fanout = 3; COMB Node = 'model1_top:u8\|model1:u6\|l1\[0\]~314'" {  } { { "D:/colorlight/light_success/simple8/db/top_cmp.qrpt" "" { Report "D:/colorlight/light_success/simple8/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/colorlight/light_success/simple8/db/colorlight.quartus_db" { Floorplan "D:/colorlight/light_success/simple8/" "" "4.374 ns" { TG:u17|ein[0] model1_top:u8|model1:u6|l1[0]~314 } "NODE_NAME" } "" } } { "model1.v" "" { Text "D:/colorlight/light_success/simple8/model1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(1.154 ns) 6.021 ns model1_top:u8\|model1:u6\|l1\[0\]~325 3 COMB LAB_11_L2 4 " "Info: 3: + IC(0.284 ns) + CELL(1.154 ns) = 6.021 ns; Loc. = LAB_11_L2; Fanout = 4; COMB Node = 'model1_top:u8\|model1:u6\|l1\[0\]~325'" {  } { { "D:/colorlight/light_success/simple8/db/top_cmp.qrpt" "" { Report "D:/colorlight/light_success/simple8/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/colorlight/light_success/simple8/db/colorlight.quartus_db" { Floorplan "D:/colorlight/light_success/simple8/" "" "1.438 ns" { model1_top:u8|model1:u6|l1[0]~314 model1_top:u8|model1:u6|l1[0]~325 } "NODE_NAME" } "" } } { "model1.v" "" { Text "D:/colorlight/light_success/simple8/model1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.899 ns) 7.915 ns model1_top:u8\|model1:u6\|l3\[0\]~226 4 COMB LAB_13_L2 1 " "Info: 4: + IC(0.995 ns) + CELL(0.899 ns) = 7.915 ns; Loc. = LAB_13_L2; Fanout = 1; COMB Node = 'model1_top:u8\|model1:u6\|l3\[0\]~226'" {  } { { "D:/colorlight/light_success/simple8/db/top_cmp.qrpt" "" { Report "D:/colorlight/light_success/simple8/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/colorlight/light_success/simple8/db/colorlight.quartus_db" { Floorplan "D:/colorlight/light_success/simple8/" "" "1.894 ns" { model1_top:u8|model1:u6|l1[0]~325 model1_top:u8|model1:u6|l3[0]~226 } "NODE_NAME" } "" } } { "model1.v" "" { Text "D:/colorlight/light_success/simple8/model1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.689 ns) 8.604 ns model1_top:u8\|model1:u6\|l3\[0\]~224 5 COMB LAB_13_L2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.689 ns) = 8.604 ns; Loc. = LAB_13_L2; Fanout = 2; COMB Node = 'model1_top:u8\|model1:u6\|l3\[0\]~224'" {  } { { "D:/colorlight/light_success/simple8/db/top_cmp.qrpt" "" { Report "D:/colorlight/light_success/simple8/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/colorlight/light_success/simple8/db/colorlight.quartus_db" { Floorplan "D:/colorlight/light_success/simple8/" "" "0.689 ns" { model1_top:u8|model1:u6|l3[0]~226 model1_top:u8|model1:u6|l3[0]~224 } "NODE_NAME" } "" } } { "model1.v" "" { Text "D:/colorlight/light_success/simple8/model1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.284 ns) + CELL(0.899 ns) 9.787 ns model1_top:u8\|model1:u6\|l3\[1\] 6 REG LAB_13_L2 2 " "Info: 6: + IC(0.284 ns) + CELL(0.899 ns) = 9.787 ns; Loc. = LAB_13_L2; Fanout = 2; REG Node = 'model1_top:u8\|model1:u6\|l3\[1\]'" {  } { { "D:/colorlight/light_success/simple8/db/top_cmp.qrpt" "" { Report "D:/colorlight/light_success/simple8/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/colorlight/light_success/simple8/db/colorlight.quartus_db" { Floorplan "D:/colorlight/light_success/simple8/" "" "1.183 ns" { model1_top:u8|model1:u6|l3[0]~224 model1_top:u8|model1:u6|l3[1] } "NODE_NAME" } "" } } { "model1.v" "" { Text "D:/colorlight/light_success/simple8/model1.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.004 ns 51.13 % " "Info: Total cell delay = 5.004 ns ( 51.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.783 ns 48.87 % " "Info: Total interconnect delay = 4.783 ns ( 48.87 % )" {  } {  } 0}  } { { "D:/colorlight/light_success/simple8/db/top_cmp.qrpt" "" { Report "D:/colorlight/light_success/simple8/db/top_cmp.qrpt" Compiler "top" "UNKNOWN" "V1" "D:/colorlight/light_success/simple8/db/colorlight.quartus_db" { Floorplan "D:/colorlight/light_success/simple8/" "" "9.787 ns" { TG:u17|ein[0] model1_top:u8|model1:u6|l1[0]~314 model1_top:u8|model1:u6|l1[0]~325 model1_top:u8|model1:u6|l3[0]~226 model1_top:u8|model1:u6|l3[0]~224 model1_top:u8|model1:u6|l3[1] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:12 " "Info: Fitter placement operations ending: elapsed time is 00:00:12" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:07 " "Info: Fitter routing operations ending: elapsed time is 00:00:07" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 17 10:07:59 2005 " "Info: Processing ended: Thu Nov 17 10:07:59 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:27 " "Info: Elapsed time: 00:00:27" {  } {  } 0}  } {  } 0}