model1_top.v

来自「一个圣诞彩灯控制芯片的vrilog源代码」· Verilog 代码 · 共 45 行

//`include "bright_clk.v"
//`include "dark_clk.v"
//`include "model2_top.v"
//`include "model3_top.v"
//`include "model4_top.v"
//`include "model5_top.v"
//`include "model6_top.v"
//`include "model7_top.v"
//`include "model1.v"
//`include "div_16500.v"
module model1_top(l1,l2,l3,l4,c,en,reset,clk_4,clk_8,clk_250k);
input  en,reset,clk_4,clk_8,clk_250k;
output [1:0] l1,l2,l3,l4;
output c;
wire [1:0] l1,l2,l3,l4;
wire c;
wire    [1:0] I0,I1,I2,I3,I4,I5,I6,I7,
              I8,I9,I10,I11,I12,I13,I14,I15,
              I16,I17,I18,I19,I20,I21,I22,I23;
wire    [5:0] cin;
wire    [5:0] ein;

//module model2(l1,l2,l3,l4,c,clk,reset,en);
model2  u0(I0,I1,I2,I3,cin[0],clk_4,reset,ein[0]);

//module model3_top(l1,l2,l3,l4,c,en,reset,clk);
model3  u1(I4,I5,I6,I7,cin[1],clk_4,reset,ein[1]);

//module model4_top(l1,l2,l3,l4,c,en,reset,clk);
model4  u2(I8,I9,I10,I11,cin[2],clk_4,reset,ein[2]);

//module model5_top(l1,l2,l3,l4,c,en,reset,clk);
model5  u3(I12,I13,I14,I15,cin[3],clk_4,reset,ein[3]);
  
//module model6_top(l1,l2,l3,l4,c,en,reset,clk_2,clk_250k);
model6  u4(I16,I17,I18,I19,cin[4],clk_8,reset,ein[4]);

//module model7(l1,l2,l3,l4,c,clk,reset,en);
model7 u5(I20,I21,I22,I23,cin[5],clk_4,reset,ein[5]);

//module model1(l1,l2,l3,l4,c,ein,reset,en,clk,cin,I);
model1  u6(l1,l2,l3,l4,c,ein,reset,en,clk_250k,cin,I0,I1,I2,I3,I4,I5,I6,I7,
           I8,I9,I10,I11,I12,I13,I14,I15,I16,I17,I18,I19,I20,I21,I22,I23);
endmodule