medium_clk.v

来自「一个圣诞彩灯控制芯片的vrilog源代码」· Verilog 代码 · 共 36 行

module medium_clk(clk_medium,reset,clk);
    output clk_medium;
    input clk,reset;
    reg clk_medium;
    reg [5:0] i;
    
    //initial             //initial??????????
    //    begin
    //        i=0;
    //        clk_bright=1;
    //    end
    
    always@(posedge clk or negedge reset)
    begin
     if(reset==1'b0)
       begin
        i<=6'b000000;
        clk_medium<=1'b0;
       end
     else
       begin
            clk_medium<=1'b0;
            if((i>=6'd10&&i<=6'd18)||(i>=6'd30&&i<=6'd31))
                clk_medium<=1'b1;
            else if(i==6'd39)
                    begin
                       clk_medium<=1'b0;
                    end 
                 else clk_medium<=1'b0; 
            if(i==6'd39)
              i<=6'b000000;
            else
              i<=i+6'b000001;          
        end
    end
endmodule