model4_huayang.v

来自「一个圣诞彩灯控制芯片的vrilog源代码」· Verilog 代码 · 共 44 行

module model4_huayang(l1,l2,l3,l4,clk_bright,clk_dark,l11,l22,l33,l44);
input clk_bright,clk_dark;
input [1:0] l11,l22,l33,l44;
output l1,l2,l3,l4;
wire [1:0] l11,l22,l33,l44;
reg l1,l2,l3,l4;

always /*@(l11 or l22 or l33 or l44) 
begin
  if(l11==1)
    l1=clk_50;
  else
    l1=1'b0;
  if(l22==1)
    l2=clk_50;
  else
    l2=1'b0;
  if(l33==1)
    l3=clk_50;
  else
    l3=1'b0;
  if(l44==1)
    l4=clk_50;
  else
    l4=1'b0;
end */

case({l11,l22,l33,l44})
  8'b00000000: begin l1=1'b0;      l2=1'b0;      l3=1'b0;      l4=1'b0;    end
  8'b01000000: begin l1=clk_dark;  l2=1'b0;      l3=1'b0;      l4=1'b0; end
  8'b10000000: begin l1=clk_bright;l2=1'b0;      l3=1'b0;      l4=1'b0;   end
  8'b01010000: begin l1=clk_dark;  l2=clk_dark;  l3=1'b0;      l4=1'b0; end
  8'b00100000: begin l1=1'b0;      l2=clk_bright;l3=1'b0;      l4=1'b0;   end
  8'b00010100: begin l1=1'b0;      l2=clk_dark;  l3=clk_dark;  l4=1'b0; end
  8'b00001000: begin l1=1'b0;      l2=1'b0;      l3=clk_bright;l4=1'b0;   end
  8'b00000101: begin l1=1'b0;      l2=1'b0;      l3=clk_dark;  l4=clk_dark; end
  8'b00000010: begin l1=1'b0;      l2=1'b0;      l3=1'b0;      l4=clk_bright;   end
  8'b01000001: begin l1=clk_dark;  l2=1'b0;      l3=1'b0;      l4=clk_dark; end
  default:     begin l1=1'b0;      l2=1'b0;      l3=1'b0;      l4=1'b0;   end  
endcase



endmodule