top.qsf

一个圣诞彩灯控制芯片的vrilog源代码

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		top_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:52:05  SEPTEMBER 20, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 5.0
set_global_assignment -name VERILOG_FILE medium_clk.v
set_global_assignment -name VERILOG_FILE div_16500.v
set_global_assignment -name VERILOG_FILE div_165000.v
set_global_assignment -name VERILOG_FILE sysclk_250k.v
set_global_assignment -name VERILOG_FILE medium1_clk.v
set_global_assignment -name VERILOG_FILE medium2_clk.v
set_global_assignment -name VERILOG_FILE model2_huayang.v
set_global_assignment -name VERILOG_FILE div_4.v
set_global_assignment -name VERILOG_FILE delay.v
set_global_assignment -name VERILOG_FILE top.v
set_global_assignment -name VERILOG_FILE bright_clk.v
set_global_assignment -name VERILOG_FILE clk_select.v
set_global_assignment -name VERILOG_FILE d.v
set_global_assignment -name VERILOG_FILE dark_clk.v
set_global_assignment -name VERILOG_FILE model1.v
set_global_assignment -name VERILOG_FILE model1_top.v
set_global_assignment -name VERILOG_FILE model2_fast.v
set_global_assignment -name VERILOG_FILE model2_select.v
set_global_assignment -name VERILOG_FILE model2_slow.v
set_global_assignment -name VERILOG_FILE model2_top.v
set_global_assignment -name VERILOG_FILE model3_fast.v
set_global_assignment -name VERILOG_FILE model3_select.v
set_global_assignment -name VERILOG_FILE model3_slow.v
set_global_assignment -name VERILOG_FILE model3_top.v
set_global_assignment -name VERILOG_FILE model3_veryslow.v
set_global_assignment -name VERILOG_FILE model4_fast.v
set_global_assignment -name VERILOG_FILE model4_select.v
set_global_assignment -name VERILOG_FILE model4_slow.v
set_global_assignment -name VERILOG_FILE model4_top.v
set_global_assignment -name VERILOG_FILE model5_3slow_inv.v
set_global_assignment -name VERILOG_FILE model5_select.v
set_global_assignment -name VERILOG_FILE model5_top.v
set_global_assignment -name VERILOG_FILE model6_fast.v
set_global_assignment -name VERILOG_FILE model6_select.v
set_global_assignment -name VERILOG_FILE model6_slow.v
set_global_assignment -name VERILOG_FILE model6_top.v
set_global_assignment -name VERILOG_FILE model7.v
set_global_assignment -name VERILOG_FILE model7_top.v
set_global_assignment -name VERILOG_FILE model8.v
set_global_assignment -name VERILOG_FILE model8_top.v
set_global_assignment -name VERILOG_FILE qudou.v
set_global_assignment -name VERILOG_FILE rs.v
set_global_assignment -name VERILOG_FILE star_twinkle.v
set_global_assignment -name VERILOG_FILE TG.v
set_global_assignment -name VERILOG_FILE div_132.v
set_global_assignment -name VERILOG_FILE div_5000.v
set_global_assignment -name VECTOR_WAVEFORM_FILE top.vwf
set_global_assignment -name VERILOG_FILE div_25.v
set_global_assignment -name VERILOG_FILE model3_huayang.v
set_global_assignment -name VERILOG_FILE model5_huayang.v
set_global_assignment -name VERILOG_FILE model7_huayang.v
set_global_assignment -name VERILOG_FILE model4_huayang.v
set_global_assignment -name VERILOG_FILE model6_huayang.v
set_global_assignment -name VERILOG_FILE sysclk.v
set_global_assignment -name VERILOG_FILE huayangclk.v
set_global_assignment -name VERILOG_FILE model7_select.v
set_global_assignment -name VERILOG_FILE medium3_clk.v
set_global_assignment -name VERILOG_FILE medium4_clk.v
set_global_assignment -name VERILOG_FILE medium5_clk.v
set_global_assignment -name VERILOG_FILE huayang.v
set_global_assignment -name VERILOG_FILE tg_count.v
set_global_assignment -name VERILOG_FILE tg_control.v
set_global_assignment -name VERILOG_FILE model2.v
set_global_assignment -name VERILOG_FILE model3.v
set_global_assignment -name VERILOG_FILE model4.v
set_global_assignment -name VERILOG_FILE model5.v
set_global_assignment -name VERILOG_FILE model6.v

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_T22 -to l1
set_location_assignment PIN_T20 -to l2
set_location_assignment PIN_T21 -to l3
set_location_assignment PIN_P1 -to l4
set_location_assignment PIN_Y8 -to reset
set_location_assignment PIN_W9 -to tg
set_location_assignment PIN_V9 -to en
set_location_assignment PIN_L6 -to zc
set_location_assignment PIN_T9 -to test

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY APEX20KE
set_global_assignment -name TOP_LEVEL_ENTITY top

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EP20K200EFC484-2X"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1