sysclk_250k.v

一个圣诞彩灯控制芯片的vrilog源代码

module sysclk_250k(clk_250k,clk,reset);
parameter num1=5'd17;
output clk_250k;
input clk,reset;
reg clk_250k;
reg [4:0] flag1;

always @(posedge clk or negedge reset)
begin
  if(reset==0)
    begin
      flag1<=5'b00000;
      clk_250k<=1'b0;
    end
  else if(flag1==num1)
         begin 
           clk_250k<=~clk_250k;
           flag1<=5'b00000;
         end
       else flag1<=flag1+5'b00001;
end
endmodule