delay.v

来自「一个圣诞彩灯控制芯片的vrilog源代码」· Verilog 代码 · 共 31 行

module delay(tg,clk,reset,i);
input tg,clk,reset;
output i;
reg i;
reg [9:0] sum,count,num;

always @(negedge tg or negedge reset or posedge clk)
begin 
    if (reset==0)
     begin
       i<=0; 
       num<=0;
    end    
     else 
          begin 
             for (sum=0; sum<10; sum=sum+1)
                begin 
                   for(count=0; count<10; count=count+1)
                           num<=num+1;
                   num<=0;
                end
                  if (tg==0)
                   if (i==3)
                       i<=0;
                      else
                        i<=i+1;
                  else sum<=0;
            end
        
end
endmodule