tg.v

一个圣诞彩灯控制芯片的vrilog源代码

module TG(l1,l2,l3,l4,ein,reset,tg,clk,I0,I1,I2,I3,I4,I5,I6,I7,
          I8,I9,I10,I11,I12,I13,I14,I15,I16,I17,I18,I19,I20,I21,
          I22,I23,I24,I25,I26,I27);
  output [1:0] l1,l2,l3,l4;
  output [6:0] ein;
  input tg,reset,clk;
  input [1:0] I0,I1,I2,I3,I4,I5,I6,I7,
              I8,I9,I10,I11,I12,I13,I14,I15,
              I16,I17,I18,I19,I20,I21,I22,I23,
              I24,I25,I26,I27;
  reg [1:0] l1,l2,l3,l4;
  reg [6:0] ein;
  wire tg,reset,clk;
  wire [1:0] I0,I1,I2,I3,I4,I5,I6,I7,
             I8,I9,I10,I11,I12,I13,I14,I15,
             I16,I17,I18,I19,I20,I21,I22,I23,
             I24,I25,I26,I27;
  reg [2:0] flag;

always@(negedge tg or negedge reset)
  begin
    if(reset==1'b0)
       begin
       flag<=3'b000;
       end
    else if(flag==3'd6)
           flag<=3'b000;
          else 
            flag<=flag+3'b001;
  end 

always@(posedge clk or negedge reset)
  begin
   if(reset==1'b0)
     begin
      ein<=7'b0000001;  
      l1<=2'b00; l2<=2'b00; l3<=2'b00; l4<=2'b00;  
     end
   else  
     begin
         case(flag)
             3'b000: ein<=7'b0000001;
             3'b001: ein<=7'b0000010;
             3'b010: ein<=7'b0000100;
             3'b011: ein<=7'b0001000;
             3'b100: ein<=7'b0010000;
             3'b101: ein<=7'b0100000;
             3'b110: ein<=7'b1000000;
             default:  ;
         endcase
          case(ein)
             7'b0000001: begin                       
                           l1<=I0; l2<=I1; l3<=I2; l4<=I3;  
                          end
             7'b0000010: begin
                           l1<=I4; l2<=I5; l3<=I6; l4<=I7;  
                          end
             7'b0000100: begin
                           l1<=I8; l2<=I9; l3<=I10; l4<=I11; 
                          end
             7'b0001000: begin
                           l1<=I12; l2<=I13; l3<=I14; l4<=I15;  
                          end
             7'b0010000: begin
                           l1<=I16; l2<=I17; l3<=I18; l4<=I19;  
                        end
             7'b0100000: begin
                          l1<=I20; l2<=I21; l3<=I22; l4<=I23;  
                        end
             7'b1000000: begin
                          l1<=I24; l2<=I25; l3<=I26; l4<=I27;  
                        end
             default:   begin
                          ein<=7'b0000001;
                        end
         endcase
        end
        end
endmodule