sysclk.v

来自「一个圣诞彩灯控制芯片的vrilog源代码」· Verilog 代码 · 共 41 行

module sysclk(clk_4,clk_8,clk_2k,clk,reset);
parameter num1=8'd249;
parameter num2=8'd249;
parameter num3=1'd1;
output clk_4,clk_8,clk_2k;
input clk,reset;
reg clk_4,clk_8,clk_2k;
reg [7:0] flag1,flag2;
reg  flag3;

always @(posedge clk or negedge reset)
begin
  if(reset==0)
    begin
      flag1<=8'b00000000;
      flag2<=8'b00000000;
      flag3<=1'b0;
      clk_4<=1'b0;
      clk_8<=1'b0;
      clk_2k<=1'b0;
    end
  else if(flag1==num1)
         begin 
           clk_2k<=~clk_2k;
           flag1<=8'b00000000;
           if(flag2==num2)
             begin
               clk_8<=~clk_8;
               flag2<=8'b00000000;
               if(flag3==num3)
                 begin
                   clk_4<=~clk_4;
                   flag3<=1'b0;
                 end
               else flag3<=flag3+1'b1; 
             end
           else flag2<=flag2+8'b00000001;  
         end
       else flag1<=flag1+8'b00000001;
end
endmodule