huayang.v

来自「一个圣诞彩灯控制芯片的vrilog源代码」· Verilog 代码 · 共 17 行

module huayang(lout,clk_bright,clk_medium,clk_dark,lin);
output lout;
input [1:0] lin;
input clk_bright,clk_medium,clk_dark;
reg lout;

always@(lin or clk_dark or clk_medium or clk_bright)
  begin
    case(lin)
      2'b00:lout=1'b0;
      2'b01:lout=clk_dark;
      2'b10:lout=clk_medium;
      2'b11:lout=clk_bright;
    endcase
  end
endmodule