model4_slow.v

一个圣诞彩灯控制芯片的vrilog源代码

module model4_slow(l1,l2,l3,l4,c,clk,reset,en);
    output [1:0] l1,l2,l3,l4;
    output c;
    input clk,reset,en;
    reg [1:0] l1,l2,l3,l4;
    reg c;
    reg [4:0] i;
       
   // initial
   //     begin
   //         i=0;
   //         l1=0;
   //         l2=0;
   //         l3=0;
   //         l4=0;
   //     end    
    
    always@(posedge clk or negedge reset)
    begin
     if(reset==1'b0)
       begin
        i<=5'b00000;
        l1<=2'b00;
        l2<=2'b00;
        l3<=2'b00;
        l4<=2'b00;
        c<=1'b0;
       end    
     else if(en==1'b1)
            begin
              case(i)
                5'd0:begin l1<=2'b01;l2<=2'b00;l3<=2'b00;l4<=2'b00;c<=1'b0;end 
                5'd1:begin l1<=2'b01;l2<=2'b00;l3<=2'b00;l4<=2'b00;c<=1'b0;end 
                5'd2:begin l1<=2'b11;l2<=2'b00;l3<=2'b00;l4<=2'b00;c<=1'b0;end
                5'd3:begin l1<=2'b11;l2<=2'b00;l3<=2'b00;l4<=2'b00;c<=1'b0;end  
                5'd4:begin l1<=2'b01;l2<=2'b01;l3<=2'b00;l4<=2'b00;c<=1'b0;end
                5'd5:begin l1<=2'b01;l2<=2'b01;l3<=2'b00;l4<=2'b00;c<=1'b0;end
                5'd6:begin l1<=2'b00;l2<=2'b11;l3<=2'b00;l4<=2'b00;c<=1'b0;end 
                5'd7:begin l1<=2'b00;l2<=2'b11;l3<=2'b00;l4<=2'b00;c<=1'b0;end 
                5'd8:begin l1<=2'b00;l2<=2'b01;l3<=2'b01;l4<=2'b00;c<=1'b0;end
                5'd9:begin l1<=2'b00;l2<=2'b01;l3<=2'b01;l4<=2'b00;c<=1'b0;end  
                5'd10:begin l1<=2'b00;l2<=2'b00;l3<=2'b11;l4<=2'b00;c<=1'b0;end 
                5'd11:begin l1<=2'b00;l2<=2'b00;l3<=2'b11;l4<=2'b00;c<=1'b0;end  
                5'd12:begin l1<=2'b00;l2<=2'b00;l3<=2'b01;l4<=2'b01;c<=1'b0;end 
                5'd13:begin l1<=2'b00;l2<=2'b00;l3<=2'b01;l4<=2'b01;c<=1'b0;end        
                5'd14:begin l1<=2'b00;l2<=2'b00;l3<=2'b00;l4<=2'b11;c<=1'b0;end 
                5'd15:begin l1<=2'b00;l2<=2'b00;l3<=2'b00;l4<=2'b11;c<=1'b0;end             
                5'd16:begin l1<=2'b01;l2<=2'b00;l3<=2'b00;l4<=2'b01;c<=1'b0;end 
                5'd17:begin l1<=2'b01;l2<=2'b00;l3<=2'b00;l4<=2'b01;c<=1'b1;end                 
                default:begin l1<=2'b00;l2<=2'b00;l3<=2'b00;l4<=2'b00;c<=1'b0;end 
              endcase            
              if(i==5'd17)
                //i<=7*n_fast;
               i<=5'b00001;
              else
               i<=i+5'b00001; 
             end
           else
              begin
                 l1<=2'b00;
                 l2<=2'b00;
                 l3<=2'b00;
                 l4<=2'b00;
                 i<=5'b00000;
                 c<=1'b0;
              end           
        end
endmodule