model1.v

来自「一个圣诞彩灯控制芯片的vrilog源代码」· Verilog 代码 · 共 63 行

module model1(l1,l2,l3,l4,c,ein,reset,en,clk,cin,I0,I1,I2,I3,I4,I5,I6,I7,
              I8,I9,I10,I11,I12,I13,I14,I15,I16,I17,I18,I19);
  output [1:0] l1,l2,l3,l4;
  output c;
  output [4:0] ein;
  input reset,en,clk;
  input [4:0] cin;
  input [1:0] I0,I1,I2,I3,I4,I5,I6,I7,
              I8,I9,I10,I11,I12,I13,I14,I15,
              I16,I17,I18,I19;
  reg [1:0] l1,l2,l3,l4;
  reg c;
  reg [4:0] ein;
  wire [4:0] cin;
  wire [1:0] I0,I1,I2,I3,I4,I5,I6,I7,
              I8,I9,I10,I11,I12,I13,I14,I15,
              I16,I17,I18,I19;

  always@(posedge clk or negedge reset)
  begin
   if(reset==0)
     begin
      ein<=5'b00001; 
      l1<=2'b00; l2<=2'b00; l3<=2'b00; l4<=2'b00; c<=1'b0;
     end
   else if(en==1'b1)
        begin
           case(cin)
             5'b00001: ein<=5'b00010;
             5'b00010: ein<=5'b00100;
             5'b00100: ein<=5'b01000;
             5'b01000: ein<=5'b10000;
             5'b10000: ein<=5'b00001;
             default:   ;
         endcase
          case(ein)
             5'b00001: begin                       
                           l1<=I0; l2<=I1; l3<=I2; l4<=I3; c<=1'b0;
                        end
             5'b00010: begin
                           l1<=I4; l2<=I5; l3<=I6; l4<=I7; c<=1'b0;
                        end
             5'b00100: begin
                           l1<=I8; l2<=I9; l3<=I10; l4<=I11; c<=1'b0;
                        end
             5'b01000: begin
                           l1<=I12; l2<=I13; l3<=I14; l4<=I15; c<=1'b0;
                        end
             5'b10000: begin
                           l1<=I16; l2<=I17; l3<=I18; l4<=I19; c<=1'b0;
                        end
             default:   begin
                          ein<=5'b00001;
                        end
         endcase
       end
     else
      begin
        ein<=5'b00000;
        l1<=2'b00; l2<=2'b00; l3<=2'b00; l4<=2'b00; c<=1'b0;
      end
end
endmodule