model2_fast.v

来自「一个圣诞彩灯控制芯片的vrilog源代码」· Verilog 代码 · 共 41 行

module model2_fast(l1,l2,l3,l4,c,clk,en,reset);
    output [1:0] l1,l2,l3,l4;
    output c;
    input clk,en,reset;
    reg [1:0] l1,l2,l3,l4;
    reg c;
    reg [2:0] i;
    
    always@(posedge clk or negedge reset)
     if (reset==0)
          begin
           l1<=2'b00; l2<=2'b00; l3<=2'b00; l4<=2'b00;
           i<=3'b000; c<=1'b0;
           end   
       else 
         begin
          if(en==1'b1)
            begin
              case(i)
                3'd0:begin l1<=2'b11;l2<=2'b11;l3<=2'b00;l4<=2'b00;c<=1'b0;end 
                3'd1:begin l1<=2'b00;l2<=2'b11;l3<=2'b00;l4<=2'b00;c<=1'b0;end
                3'd2:begin l1<=2'b00;l2<=2'b11;l3<=2'b11;l4<=2'b00;c<=1'b0;end 
                3'd3:begin l1<=2'b00;l2<=2'b00;l3<=2'b11;l4<=2'b00;c<=1'b0;end
                3'd4:begin l1<=2'b00;l2<=2'b00;l3<=2'b11;l4<=2'b11;c<=1'b0;end 
                3'd5:begin l1<=2'b00;l2<=2'b00;l3<=2'b00;l4<=2'b11;c<=1'b0;end         
                3'd6:begin l1<=2'b00;l2<=2'b00;l3<=2'b00;l4<=2'b00;c<=1'b1;end            
              default:begin l1<=2'b00;l2<=2'b00;l3<=2'b00;l4<=2'b00;c<=1'b0;end 
              endcase
              if(i==3'd6)
                i<=3'b000;
              else 
                i<=i+3'b001;   
            end
          else 
            begin
             l1<=2'b00; l2<=2'b00; l3<=2'b00; l4<=2'b00;
             i<=3'b000; c<=1'b0;
            end
   end
endmodule