model5_select.v

一个圣诞彩灯控制芯片的vrilog源代码

module model5_select(l1,l2,l3,l4,c,en1,en2,en3,reset,en,clk,c1,c2,c3,l11,l12,l13,l14,l21,l22,l23,l24,l31,l32,l33,l34);
  output [1:0] l1,l2,l3,l4;
  output c,en1,en2,en3;
  input reset,en,clk,c1,c2,c3;
  input [1:0] l11,l12,l13,l14,l21,l22,l23,l24,l31,l32,l33,l34;
  reg [1:0] l1,l2,l3,l4;
  reg c,en1,en2,en3;
  wire [1:0] l11,l12,l13,l14,l21,l22,l23,l24,l31,l32,l33,l34;
  reg [2:0] i;

  always@(posedge clk or negedge reset)
  begin
   if(reset==1'b0)
     begin
      i<=3'b000; en1<=1'b0; en2<=1'b0; en3<=1'b0; 
      l1<=2'b00; l2<=2'b00; l3<=2'b00; l4<=2'b00; c<=1'b0;
     end
   else if(en==1'b1)
        begin
         if(i<3'd1)
           begin
             en1<=1'b1; en2<=1'b0; en3<=1'b0; 
             l1<=l11; l2<=l12; l3<=l13; l4<=l14; c<=1'b0;
             if(c1==1'b1) 
               i<=i+3'b001;
          end
        else if(i<3'd3)
           begin
             en1<=1'b0; en2<=1'b1; en3<=1'b0; 
             l1<=l21; l2<=l22; l3<=l23; l4<=l24; c<=1'b0;
             if(c2==1'b1)
               i<=i+3'b001;
           end
              else if(i<3'd4)
                     begin
                      en1<=1'b0; en2<=1'b0; en3<=1'b1; 
                      l1<=l31; l2<=l32; l3<=l33; l4<=l34; c<=1'b0;
                      if(c3==1'b1)
                        i<=i+3'b001;
                     end
                    else if(i<3'd6)
                           begin
                             en1<=1'b0; en2<=1'b1; en3<=1'b0; 
                             l1<=l21; l2<=l22; l3<=l23; l4<=l24; c<=1'b0;
                             if(c2==1'b1)
                             i<=i+3'b001;
                           end
                         else if(i==3'd6)
                                 begin
                                   en1<=1'b0; en2<=1'b0; en3<=1'b0; 
                                   l1<=2'b00; l2<=2'b00; l3<=2'b00; l4<=2'b00; c<=1'b1;
                                   i<=3'b000;
                                 end
       end
else
  begin
    en1<=1'b0; en2<=1'b0; en3<=1'b0; 
    l1<=2'b00; l2<=2'b00; l3<=2'b00; l4<=2'b00; c<=1'b0;
    i<=3'b000;
  end
end

endmodule