model1.v

一个圣诞彩灯控制芯片的vrilog源代码

module model1(l1,l2,l3,l4,c,ein,reset,en,clk,cin,I0,I1,I2,I3,I4,I5,I6,I7,
              I8,I9,I10,I11,I12,I13,I14,I15,I16,I17,I18,I19,I20,I21,I22,I23);
  output [1:0] l1,l2,l3,l4;
  output c;
  output [5:0] ein;
  input reset,en,clk;
  input [5:0] cin;
  input [1:0] I0,I1,I2,I3,I4,I5,I6,I7,
              I8,I9,I10,I11,I12,I13,I14,I15,
              I16,I17,I18,I19,I20,I21,I22,I23;
  reg [1:0] l1,l2,l3,l4;
  reg c;
  reg [5:0] ein;
  wire [5:0] cin;
  wire [1:0] I0,I1,I2,I3,I4,I5,I6,I7,
              I8,I9,I10,I11,I12,I13,I14,I15,
              I16,I17,I18,I19,I20,I21,I22,I23;

  always@(posedge clk or negedge reset)
  begin
   if(reset==0)
     begin
      ein<=6'b000001; 
      l1<=2'b00; l2<=2'b00; l3<=2'b00; l4<=2'b00; c<=1'b0;
     end
   else if(en==1'b1)
        begin
           case(cin)
             6'b000001: ein<=6'b000010;
             6'b000010: ein<=6'b000100;
             6'b000100: ein<=6'b001000;
             6'b001000: ein<=6'b010000;
             6'b010000: ein<=6'b100000;
             6'b100000: ein<=6'b000001;
             default:   ;
         endcase
          case(ein)
             6'b000001: begin                       
                           l1<=I0; l2<=I1; l3<=I2; l4<=I3; c<=1'b0;
                        end
             6'b000010: begin
                           l1<=I4; l2<=I5; l3<=I6; l4<=I7; c<=1'b0;
                        end
             6'b000100: begin
                           l1<=I8; l2<=I9; l3<=I10; l4<=I11; c<=1'b0;
                        end
             6'b001000: begin
                           l1<=I12; l2<=I13; l3<=I14; l4<=I15; c<=1'b0;
                        end
             6'b010000: begin
                           l1<=I16; l2<=I17; l3<=I18; l4<=I19; c<=1'b0;
                        end
             6'b100000: begin
                          l1<=I20; l2<=I21; l3<=I22; l4<=I23; c<=1'b1;
                        end
             default:   begin
                          ein<=6'b000001;
                        end
         endcase
       end
     else
      begin
        ein<=6'b000000;
        l1<=2'b00; l2<=2'b00; l3<=2'b00; l4<=2'b00; c<=1'b0;
      end
end
endmodule