top.map.rpt

一个圣诞彩灯控制芯片的vrilog源代码

    Info: Found entity 1: model6_select
Info: Found 1 design units, including 1 entities, in source file model6_slow.v
    Info: Found entity 1: model6_slow
Info: Found 1 design units, including 1 entities, in source file model6_top.v
    Info: Found entity 1: model6_top
Info: Found 1 design units, including 1 entities, in source file model7.v
    Info: Found entity 1: model7
Info: Found 1 design units, including 1 entities, in source file model7_top.v
    Info: Found entity 1: model7_top
Info: Found 1 design units, including 1 entities, in source file model8.v
    Info: Found entity 1: model8
Info: Found 1 design units, including 1 entities, in source file model8_top.v
    Info: Found entity 1: model8_top
Info: Found 1 design units, including 1 entities, in source file qudou.v
    Info: Found entity 1: qudou
Info: Found 1 design units, including 1 entities, in source file rs.v
    Info: Found entity 1: rs
Info: Found 1 design units, including 1 entities, in source file star_twinkle.v
    Info: Found entity 1: star_twinkle
Info: Found 1 design units, including 1 entities, in source file TG.v
    Info: Found entity 1: TG
Info: Found 1 design units, including 1 entities, in source file div_132.v
    Info: Found entity 1: div_132
Info: Found 1 design units, including 1 entities, in source file div_5000.v
    Info: Found entity 1: div_5000
Info: Found 1 design units, including 1 entities, in source file div_25.v
    Info: Found entity 1: div_25
Info: Found 1 design units, including 1 entities, in source file model3_huayang.v
    Info: Found entity 1: model3_huayang
Info: Found 1 design units, including 1 entities, in source file model5_huayang.v
    Info: Found entity 1: model5_huayang
Info: Found 1 design units, including 1 entities, in source file model7_huayang.v
    Info: Found entity 1: model7_huayang
Info: Found 1 design units, including 1 entities, in source file model4_huayang.v
    Info: Found entity 1: model4_huayang
Info: Found 1 design units, including 1 entities, in source file model6_huayang.v
    Info: Found entity 1: model6_huayang
Info: Found 1 design units, including 1 entities, in source file sysclk.v
    Info: Found entity 1: sysclk
Info: Found 1 design units, including 1 entities, in source file huayangclk.v
    Info: Found entity 1: huayangclk
Info: Found 1 design units, including 1 entities, in source file model7_select.v
    Info: Found entity 1: model7_select
Info: Found 1 design units, including 1 entities, in source file medium3_clk.v
    Info: Found entity 1: medium3_clk
Info: Found 1 design units, including 1 entities, in source file medium4_clk.v
    Info: Found entity 1: medium4_clk
Info: Found 1 design units, including 1 entities, in source file medium5_clk.v
    Info: Found entity 1: medium5_clk
Info: Found 1 design units, including 1 entities, in source file huayang.v
    Info: Found entity 1: huayang
Info: Found 1 design units, including 1 entities, in source file tg_count.v
    Info: Found entity 1: tg_count
Info: Found 1 design units, including 1 entities, in source file tg_control.v
    Info: Found entity 1: tg_control
Info: Found 1 design units, including 1 entities, in source file model2.v
    Info: Found entity 1: model2
Info: Found 1 design units, including 1 entities, in source file model3.v
    Info: Found entity 1: model3
Info: Found 1 design units, including 1 entities, in source file model4.v
    Info: Found entity 1: model4
Info: Found 1 design units, including 1 entities, in source file model5.v
    Info: Found entity 1: model5
Info: Found 1 design units, including 1 entities, in source file model6.v
    Info: Found entity 1: model6
Info: Elaborating entity "top" for the top level hierarchy
Info: (10035) Verilog HDL or VHDL information at top.v(47): object "clk_2" declared but not used
Info: Elaborating entity "clk_select" for hierarchy "clk_select:u22"
Info: Elaborating entity "sysclk_250k" for hierarchy "sysclk_250k:u23"
Info: Elaborating entity "sysclk" for hierarchy "sysclk:u0"
Info: Elaborating entity "bright_clk" for hierarchy "bright_clk:u1"
Info: Elaborating entity "medium_clk" for hierarchy "medium_clk:u6"
Info: Elaborating entity "dark_clk" for hierarchy "dark_clk:u7"
Info: Elaborating entity "model1_top" for hierarchy "model1_top:u8"
Info: Elaborating entity "model2" for hierarchy "model1_top:u8|model2:u0"
Info: Elaborating entity "model3" for hierarchy "model1_top:u8|model3:u1"
Info: Elaborating entity "model4" for hierarchy "model1_top:u8|model4:u2"
Info: Elaborating entity "model5" for hierarchy "model1_top:u8|model5:u3"
Info: Elaborating entity "model6" for hierarchy "model1_top:u8|model6:u4"
Info: Elaborating entity "model7" for hierarchy "model1_top:u8|model7:u5"
Info: Elaborating entity "model1" for hierarchy "model1_top:u8|model1:u6"
Info: Verilog HDL Case Statement information at model1.v(28): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement
Info: Verilog HDL Case Statement information at model1.v(37): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement
Info: Elaborating entity "model8" for hierarchy "model8:u15"
Info: Elaborating entity "qudou" for hierarchy "qudou:u16"
Info: Elaborating entity "d" for hierarchy "qudou:u16|d:m0"
Info: Elaborating entity "rs" for hierarchy "qudou:u16|rs:m4"
Info: Elaborating entity "TG" for hierarchy "TG:u17"
Info: Verilog HDL Case Statement information at TG.v(52): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement
Info: Elaborating entity "huayang" for hierarchy "huayang:u18"
Info: Duplicate registers merged to single register
    Info: Duplicate register "model8:u15|l1[1]" merged to single register "model8:u15|l1[0]"
    Info: Duplicate register "model8:u15|l2[1]" merged to single register "model8:u15|l1[0]"
    Info: Duplicate register "model8:u15|l2[0]" merged to single register "model8:u15|l1[0]"
    Info: Duplicate register "model8:u15|l3[1]" merged to single register "model8:u15|l1[0]"
    Info: Duplicate register "model8:u15|l3[0]" merged to single register "model8:u15|l1[0]"
    Info: Duplicate register "model8:u15|l4[1]" merged to single register "model8:u15|l1[0]"
    Info: Duplicate register "model8:u15|l4[0]" merged to single register "model8:u15|l1[0]"
    Info: Duplicate register "model7:u14|l1[0]" merged to single register "model7:u14|l1[1]"
    Info: Duplicate register "model7:u14|l3[1]" merged to single register "model7:u14|l1[1]"
    Info: Duplicate register "model7:u14|l3[0]" merged to single register "model7:u14|l1[1]"
    Info: Duplicate register "model7:u14|l2[0]" merged to single register "model7:u14|l2[1]"
    Info: Duplicate register "model7:u14|l4[1]" merged to single register "model7:u14|l2[1]"
    Info: Duplicate register "model7:u14|l4[0]" merged to single register "model7:u14|l2[1]"
    Info: Duplicate register "model6:u13|l2[1]" merged to single register "model6:u13|l1[1]"
    Info: Duplicate register "model6:u13|l3[1]" merged to single register "model6:u13|l1[1]"
    Info: Duplicate register "model6:u13|l4[1]" merged to single register "model6:u13|l1[1]"
    Info: Duplicate register "model6:u13|l2[0]" merged to single register "model6:u13|l1[0]"
    Info: Duplicate register "model6:u13|l3[0]" merged to single register "model6:u13|l1[0]"
    Info: Duplicate register "model6:u13|l4[0]" merged to single register "model6:u13|l1[0]"
    Info: Duplicate register "model5:u12|l1[0]" merged to single register "model5:u12|l1[1]"
    Info: Duplicate register "model5:u12|l2[0]" merged to single register "model5:u12|l2[1]"
    Info: Duplicate register "model5:u12|l3[0]" merged to single register "model5:u12|l3[1]"
    Info: Duplicate register "model5:u12|l4[0]" merged to single register "model5:u12|l4[1]"
    Info: Duplicate register "model3:u10|l1[0]" merged to single register "model3:u10|l1[1]"
    Info: Duplicate register "model3:u10|l2[0]" merged to single register "model3:u10|l2[1]"
    Info: Duplicate register "model3:u10|l3[0]" merged to single register "model3:u10|l3[1]"
    Info: Duplicate register "model3:u10|l4[0]" merged to single register "model3:u10|l4[1]"
    Info: Duplicate register "model2:u9|l1[1]" merged to single register "model2:u9|l1[0]"
    Info: Duplicate register "model2:u9|l2[0]" merged to single register "model2:u9|l2[1]"
    Info: Duplicate register "model2:u9|l3[0]" merged to single register "model2:u9|l3[1]"
    Info: Duplicate register "model2:u9|l4[0]" merged to single register "model2:u9|l4[1]"
    Info: Duplicate register "model1_top:u8|model7:u5|l1[0]" merged to single register "model1_top:u8|model7:u5|l1[1]"
    Info: Duplicate register "model1_top:u8|model7:u5|l3[1]" merged to single register "model1_top:u8|model7:u5|l1[1]"
    Info: Duplicate register "model1_top:u8|model7:u5|l3[0]" merged to single register "model1_top:u8|model7:u5|l1[1]"
    Info: Duplicate register "model1_top:u8|model7:u5|l2[0]" merged to single register "model1_top:u8|model7:u5|l2[1]"
    Info: Duplicate register "model1_top:u8|model7:u5|l4[1]" merged to single register "model1_top:u8|model7:u5|l2[1]"
    Info: Duplicate register "model1_top:u8|model7:u5|l4[0]" merged to single register "model1_top:u8|model7:u5|l2[1]"
    Info: Duplicate register "model1_top:u8|model6:u4|l2[1]" merged to single register "model1_top:u8|model6:u4|l1[1]"
    Info: Duplicate register "model1_top:u8|model6:u4|l3[1]" merged to single register "model1_top:u8|model6:u4|l1[1]"
    Info: Duplicate register "model1_top:u8|model6:u4|l4[1]" merged to single register "model1_top:u8|model6:u4|l1[1]"
    Info: Duplicate register "model1_top:u8|model6:u4|l2[0]" merged to single register "model1_top:u8|model6:u4|l1[0]"
    Info: Duplicate register "model1_top:u8|model6:u4|l3[0]" merged to single register "model1_top:u8|model6:u4|l1[0]"
    Info: Duplicate register "model1_top:u8|model6:u4|l4[0]" merged to single register "model1_top:u8|model6:u4|l1[0]"
    Info: Duplicate register "model1_top:u8|model5:u3|l1[0]" merged to single register "model1_top:u8|model5:u3|l1[1]"
    Info: Duplicate register "model1_top:u8|model5:u3|l2[0]" merged to single register "model1_top:u8|model5:u3|l2[1]"
    Info: Duplicate register "model1_top:u8|model5:u3|l3[0]" merged to single register "model1_top:u8|model5:u3|l3[1]"
    Info: Duplicate register "model1_top:u8|model5:u3|l4[0]" merged to single register "model1_top:u8|model5:u3|l4[1]"
    Info: Duplicate register "model1_top:u8|model3:u1|l1[0]" merged to single register "model1_top:u8|model3:u1|l1[1]"
    Info: Duplicate register "model1_top:u8|model3:u1|l2[0]" merged to single register "model1_top:u8|model3:u1|l2[1]"
    Info: Duplicate register "model1_top:u8|model3:u1|l3[0]" merged to single register "model1_top:u8|model3:u1|l3[1]"
    Info: Duplicate register "model1_top:u8|model3:u1|l4[0]" merged to single register "model1_top:u8|model3:u1|l4[1]"
    Info: Duplicate register "model1_top:u8|model2:u0|l1[1]" merged to single register "model1_top:u8|model2:u0|l1[0]"
    Info: Duplicate register "model1_top:u8|model2:u0|l2[0]" merged to single register "model1_top:u8|model2:u0|l2[1]"
    Info: Duplicate register "model1_top:u8|model2:u0|l3[0]" merged to single register "model1_top:u8|model2:u0|l3[1]"
    Info: Duplicate register "model1_top:u8|model2:u0|l4[0]" merged to single register "model1_top:u8|model2:u0|l4[1]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "medium_clk:u6|i[0]" merged to single register "dark_clk:u7|i[0]"
    Info: Duplicate register "bright_clk:u1|i[0]" merged to single register "dark_clk:u7|i[0]"
    Info: Duplicate register "sysclk:u0|clk_2k" merged to single register "sysclk:u0|flag2[0]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "sysclk:u0|flag3" merged to single register "sysclk:u0|clk_8"
Info: Duplicate registers merged to single register
    Info: Duplicate register "medium_clk:u6|i[1]" merged to single register "dark_clk:u7|i[1]"
    Info: Duplicate register "medium_clk:u6|i[2]" merged to single register "dark_clk:u7|i[2]"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning: Reduced register "TG:u17|flag[3]" with stuck data_in port to stuck value GND
Info: Implemented 501 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 4 output pins
    Info: Implemented 492 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Thu Nov 17 10:07:30 2005
    Info: Elapsed time: 00:00:13