📄 top.map.rpt
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+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------+
; |top ; 492 (0) ; 192 ; 0 ; 9 ; 0 ; 300 (0) ; 34 (0) ; 158 (0) ; 89 (0) ; |top ;
; |TG:u17| ; 70 (70) ; 19 ; 0 ; 0 ; 0 ; 51 (51) ; 11 (11) ; 8 (8) ; 0 (0) ; |top|TG:u17 ;
; |bright_clk:u1| ; 13 (13) ; 6 ; 0 ; 0 ; 0 ; 7 (7) ; 3 (3) ; 3 (3) ; 5 (5) ; |top|bright_clk:u1 ;
; |clk_select:u22| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|clk_select:u22 ;
; |dark_clk:u7| ; 15 (15) ; 7 ; 0 ; 0 ; 0 ; 8 (8) ; 4 (4) ; 3 (3) ; 6 (6) ; |top|dark_clk:u7 ;
; |huayang:u18| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|huayang:u18 ;
; |huayang:u19| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|huayang:u19 ;
; |huayang:u20| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|huayang:u20 ;
; |huayang:u21| ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 0 (0) ; 0 (0) ; |top|huayang:u21 ;
; |medium_clk:u6| ; 12 (12) ; 4 ; 0 ; 0 ; 0 ; 8 (8) ; 1 (1) ; 3 (3) ; 5 (5) ; |top|medium_clk:u6 ;
; |model1_top:u8| ; 188 (0) ; 74 ; 0 ; 0 ; 0 ; 114 (0) ; 1 (0) ; 73 (0) ; 26 (0) ; |top|model1_top:u8 ;
; |model1:u6| ; 54 (54) ; 14 ; 0 ; 0 ; 0 ; 40 (40) ; 0 (0) ; 14 (14) ; 0 (0) ; |top|model1_top:u8|model1:u6 ;
; |model2:u0| ; 23 (23) ; 10 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 10 (10) ; 5 (5) ; |top|model1_top:u8|model2:u0 ;
; |model3:u1| ; 19 (19) ; 10 ; 0 ; 0 ; 0 ; 9 (9) ; 0 (0) ; 10 (10) ; 5 (5) ; |top|model1_top:u8|model3:u1 ;
; |model4:u2| ; 42 (42) ; 15 ; 0 ; 0 ; 0 ; 27 (27) ; 1 (1) ; 14 (14) ; 6 (6) ; |top|model1_top:u8|model4:u2 ;
; |model5:u3| ; 21 (21) ; 10 ; 0 ; 0 ; 0 ; 11 (11) ; 0 (0) ; 10 (10) ; 5 (5) ; |top|model1_top:u8|model5:u3 ;
; |model6:u4| ; 18 (18) ; 8 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 8 (8) ; 5 (5) ; |top|model1_top:u8|model6:u4 ;
; |model7:u5| ; 11 (11) ; 7 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 7 (7) ; 0 (0) ; |top|model1_top:u8|model7:u5 ;
; |model2:u9| ; 22 (22) ; 9 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 9 (9) ; 5 (5) ; |top|model2:u9 ;
; |model3:u10| ; 18 (18) ; 9 ; 0 ; 0 ; 0 ; 9 (9) ; 0 (0) ; 9 (9) ; 5 (5) ; |top|model3:u10 ;
; |model4:u11| ; 41 (41) ; 14 ; 0 ; 0 ; 0 ; 27 (27) ; 1 (1) ; 13 (13) ; 6 (6) ; |top|model4:u11 ;
; |model5:u12| ; 20 (20) ; 9 ; 0 ; 0 ; 0 ; 11 (11) ; 0 (0) ; 9 (9) ; 5 (5) ; |top|model5:u12 ;
; |model6:u13| ; 17 (17) ; 7 ; 0 ; 0 ; 0 ; 10 (10) ; 0 (0) ; 7 (7) ; 5 (5) ; |top|model6:u13 ;
; |model7:u14| ; 10 (10) ; 6 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 6 (6) ; 0 (0) ; |top|model7:u14 ;
; |model8:u15| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |top|model8:u15 ;
; |qudou:u16| ; 3 (0) ; 3 ; 0 ; 0 ; 0 ; 0 (0) ; 2 (0) ; 1 (0) ; 0 (0) ; |top|qudou:u16 ;
; |d:m0| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |top|qudou:u16|d:m0 ;
; |d:m1| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |top|qudou:u16|d:m1 ;
; |rs:m4| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; |top|qudou:u16|rs:m4 ;
; |sysclk:u0| ; 40 (40) ; 18 ; 0 ; 0 ; 0 ; 22 (22) ; 6 (6) ; 12 (12) ; 16 (16) ; |top|sysclk:u0 ;
; |sysclk_250k:u23| ; 13 (13) ; 6 ; 0 ; 0 ; 0 ; 7 (7) ; 4 (4) ; 2 (2) ; 5 (5) ; |top|sysclk_250k:u23 ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 192 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 189 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 13 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; bright_clk:u1|clk_bright ; 4 ;
; TG:u17|ein[0] ; 11 ;
; model1_top:u8|model1:u6|ein[0] ; 17 ;
; Total number of inverted registers = 3 ; ;
+----------------------------------------+---------+
+--------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sysclk_250k:u23 ;
+----------------+-------+-------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-------------------------------------+
; num1 ; 10001 ; Binary ;
+----------------+-------+-------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------+
; Parameter Settings for User Entity Instance: sysclk:u0 ;
+----------------+----------+----------------------------+
; Parameter Name ; Value ; Type ;
+----------------+----------+----------------------------+
; num1 ; 11111001 ; Binary ;
; num2 ; 11111001 ; Binary ;
; num3 ; 1 ; Binary ;
+----------------+----------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/colorlight/light_success/simple8/top.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Thu Nov 17 10:07:17 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off colorlight -c top
Info: Found 1 design units, including 1 entities, in source file medium_clk.v
Info: Found entity 1: medium_clk
Info: Found 1 design units, including 1 entities, in source file div_16500.v
Info: Found entity 1: div_16500
Info: Found 1 design units, including 1 entities, in source file div_165000.v
Info: Found entity 1: div_165000
Info: Found 1 design units, including 1 entities, in source file sysclk_250k.v
Info: Found entity 1: sysclk_250k
Info: Found 1 design units, including 1 entities, in source file medium1_clk.v
Info: Found entity 1: medium1_clk
Info: Found 1 design units, including 1 entities, in source file medium2_clk.v
Info: Found entity 1: medium2_clk
Info: Found 1 design units, including 1 entities, in source file model2_huayang.v
Info: Found entity 1: model2_huayang
Info: Found 1 design units, including 1 entities, in source file div_4.v
Info: Found entity 1: div_4
Info: Found 1 design units, including 1 entities, in source file delay.v
Info: Found entity 1: delay
Info: Found 1 design units, including 1 entities, in source file top.v
Info: Found entity 1: top
Info: Found 1 design units, including 1 entities, in source file bright_clk.v
Info: Found entity 1: bright_clk
Info: Found 1 design units, including 1 entities, in source file clk_select.v
Info: Found entity 1: clk_select
Info: Found 1 design units, including 1 entities, in source file d.v
Info: Found entity 1: d
Info: Found 1 design units, including 1 entities, in source file dark_clk.v
Info: Found entity 1: dark_clk
Info: Found 1 design units, including 1 entities, in source file model1.v
Info: Found entity 1: model1
Info: Found 1 design units, including 1 entities, in source file model1_top.v
Info: Found entity 1: model1_top
Info: Found 1 design units, including 1 entities, in source file model2_fast.v
Info: Found entity 1: model2_fast
Info: Found 1 design units, including 1 entities, in source file model2_select.v
Info: Found entity 1: model2_select
Info: Found 1 design units, including 1 entities, in source file model2_slow.v
Info: Found entity 1: model2_slow
Info: Found 1 design units, including 1 entities, in source file model2_top.v
Info: Found entity 1: model2_top
Info: Found 1 design units, including 1 entities, in source file model3_fast.v
Info: Found entity 1: model3_fast
Info: Found 1 design units, including 1 entities, in source file model3_select.v
Info: Found entity 1: model3_select
Info: Found 1 design units, including 1 entities, in source file model3_slow.v
Info: Found entity 1: model3_slow
Info: Found 1 design units, including 1 entities, in source file model3_top.v
Info: Found entity 1: model3_top
Info: Found 1 design units, including 1 entities, in source file model3_veryslow.v
Info: Found entity 1: model3_veryslow
Info: Found 1 design units, including 1 entities, in source file model4_fast.v
Info: Found entity 1: model4_fast
Info: Found 1 design units, including 1 entities, in source file model4_select.v
Info: Found entity 1: model4_select
Info: Found 1 design units, including 1 entities, in source file model4_slow.v
Info: Found entity 1: model4_slow
Info: Found 1 design units, including 1 entities, in source file model4_top.v
Info: Found entity 1: model4_top
Info: Found 1 design units, including 1 entities, in source file model5_3slow_inv.v
Info: Found entity 1: model5_3slow_inv
Info: Found 1 design units, including 1 entities, in source file model5_select.v
Info: Found entity 1: model5_select
Info: Found 1 design units, including 1 entities, in source file model5_top.v
Info: Found entity 1: model5_top
Info: Found 1 design units, including 1 entities, in source file model6_fast.v
Info: Found entity 1: model6_fast
Info: Found 1 design units, including 1 entities, in source file model6_select.v
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