huayangclk.v

一个圣诞彩灯控制芯片的vrilog源代码

module huayangclk(clk_bright,clk_medium,clk_dark,reset,clk_250k);
parameter count=40;
parameter count1=count/4;
parameter count2=3*count/4;
output clk_bright,clk_medium,clk_dark;
input reset,clk_250k;
reg clk_bright,clk_medium,clk_dark;
reg [5:0] flag1,flag2,flag3;

always @(posedge clk_250k or negedge reset)
begin
  if(reset==0)
      begin
       flag1<=6'b000000;
       flag2<=6'b000000;
       flag3<=6'b000000;
       clk_bright<=1'b1;
       clk_medium<=1'b0;
       clk_dark<=1'b0;
      end
  else
        begin  
            clk_bright<=1'b1;
            clk_medium<=1'b0;
            clk_dark<=1'b0;
            if((flag1>=count1&&flag1<=count1+2)||flag1==count2)
                clk_bright<=1'b0;
            else  clk_bright<=1'b1;
            if((flag2>=count1&&flag2<=count1+8)||(flag2>=count2&&flag2<=count2+1))
                clk_medium<=1'b1;
            else  clk_medium<=1'b0;
            if((flag3>=count1&&flag3<=count1+1)||(flag3>=count2&&flag3<=count2+1))
                clk_dark<=1'b1;
            else  clk_dark<=1'b0;
        end
  if(flag1==count-1)
    flag1<=6'b000000;
  else
    flag1<=flag1+6'b000001;
  if(flag2==count-1)
    flag2<=6'b000000;
  else
    flag2<=flag2+6'b000001;
  if(flag3==count-1)
    flag3<=6'b000000;
  else
    flag3<=flag3+6'b000001;
end
endmodule