div_165000.v

来自「一个圣诞彩灯控制芯片的vrilog源代码」· Verilog 代码 · 共 38 行

module div_165000(clk_200,clk,reset);
parameter num1=5'd29;
parameter num2=6'd49;
parameter num3=7'd109;
output clk_200;
input clk,reset;
reg clk_200;
reg [4:0] flag1;
reg [5:0] flag2;
reg [6:0] flag3;

always @(posedge clk)
begin
  if(reset)
    begin
      flag1<=5'b00000;
      flag2<=6'b000000;
      flag3<=7'b0000000;
      clk_200<=1'b0;
    end
  else if(flag1==num1)
         begin
           flag1<=5'b00000;
           if(flag2==num2)
             begin
               flag2<=6'b000000;
               if(flag3==num3)
                 begin
                   flag3<=7'b0000000;
                   clk_200<=~clk_200;
                 end
               else flag3<=flag3+7'b0000001; 
             end
           else flag2<=flag2+6'b000001;  
         end
       else flag1<=flag1+5'b00001;
end
endmodule