speaker.map.qmsg

verilog语言写的杨声器!

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jan 18 19:57:35 2008 " "Info: Processing started: Fri Jan 18 19:57:35 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off speaker -c speaker " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off speaker -c speaker" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "speaker.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file speaker.v" { { "Info" "ISGN_ENTITY_NAME" "1 music " "Info: Found entity 1: music" {  } { { "speaker.v" "" { Text "D:/FPGAtest/speaker/speaker.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "music " "Info: Elaborating entity \"music\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 28 speaker.v(6) " "Warning: Verilog HDL assignment warning at speaker.v(6): truncated value with size 32 to match size of target (28)" {  } { { "speaker.v" "" { Text "D:/FPGAtest/speaker/speaker.v" 6 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 15 speaker.v(13) " "Warning: Verilog HDL assignment warning at speaker.v(13): truncated value with size 32 to match size of target (15)" {  } { { "speaker.v" "" { Text "D:/FPGAtest/speaker/speaker.v" 13 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "74 " "Info: Implemented 74 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "72 " "Info: Implemented 72 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jan 18 19:57:42 2008 " "Info: Processing ended: Fri Jan 18 19:57:42 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0}  } {  } 0}