speaker.tan.rpt

verilog语言写的杨声器!

; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[2]  ; counter[8]   ; clk        ; clk      ; None                        ; None                      ; 3.284 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[3]  ; counter[9]   ; clk        ; clk      ; None                        ; None                      ; 3.283 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[2]  ; counter[14]  ; clk        ; clk      ; None                        ; None                      ; 3.282 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[13] ; counter[4]   ; clk        ; clk      ; None                        ; None                      ; 3.270 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[13] ; counter[1]   ; clk        ; clk      ; None                        ; None                      ; 3.269 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[12] ; counter[14]  ; clk        ; clk      ; None                        ; None                      ; 3.267 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[7]  ; counter[14]  ; clk        ; clk      ; None                        ; None                      ; 3.265 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[14] ; counter[10]  ; clk        ; clk      ; None                        ; None                      ; 3.235 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[14] ; counter[7]   ; clk        ; clk      ; None                        ; None                      ; 3.233 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[14] ; counter[6]   ; clk        ; clk      ; None                        ; None                      ; 3.232 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[14] ; counter[12]  ; clk        ; clk      ; None                        ; None                      ; 3.230 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; tone[22]    ; counter[11]  ; clk        ; clk      ; None                        ; None                      ; 3.219 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[12] ; counter[8]   ; clk        ; clk      ; None                        ; None                      ; 3.210 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[1]  ; counter[9]   ; clk        ; clk      ; None                        ; None                      ; 3.210 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[12] ; counter[9]   ; clk        ; clk      ; None                        ; None                      ; 3.209 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[1]  ; counter[8]   ; clk        ; clk      ; None                        ; None                      ; 3.208 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[1]  ; counter[14]  ; clk        ; clk      ; None                        ; None                      ; 3.206 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; tone[25]    ; counter[6]   ; clk        ; clk      ; None                        ; None                      ; 3.197 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; tone[25]    ; counter[12]  ; clk        ; clk      ; None                        ; None                      ; 3.194 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[14] ; counter[14]  ; clk        ; clk      ; None                        ; None                      ; 3.191 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[2]  ; counter[13]  ; clk        ; clk      ; None                        ; None                      ; 3.187 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[7]  ; counter[13]  ; clk        ; clk      ; None                        ; None                      ; 3.170 ns                ;
; N/A                                     ; Restricted to 275.03 MHz ( period = 3.636 ns )      ; counter[13] ; counter[3]   ; clk        ; clk      ; None                        ; None                      ; 3.167 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;             ;              ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+-------------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 7.602 ns   ; speaker~reg0 ; speaker ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Jan 18 19:58:02 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off speaker -c speaker --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 195.77 MHz between source register "counter[4]" and destination register "speaker~reg0" (period= 5.108 ns)
    Info: + Longest register to register delay is 4.847 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y14_N5; Fanout = 4; REG Node = 'counter[4]'
        Info: 2: + IC(1.167 ns) + CELL(0.590 ns) = 1.757 ns; Loc. = LC_X33_Y13_N1; Fanout = 1; COMB Node = 'reduce_nor~101'
        Info: 3: + IC(0.437 ns) + CELL(0.590 ns) = 2.784 ns; Loc. = LC_X33_Y13_N8; Fanout = 15; COMB Node = 'reduce_nor~103'
        Info: 4: + IC(1.196 ns) + CELL(0.867 ns) = 4.847 ns; Loc. = LC_X31_Y13_N3; Fanout = 2; REG Node = 'speaker~reg0'
        Info: Total cell delay = 2.047 ns ( 42.23 % )
        Info: Total interconnect delay = 2.800 ns ( 57.77 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.962 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 44; CLK Node = 'clk'
            Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X31_Y13_N3; Fanout = 2; REG Node = 'speaker~reg0'
            Info: Total cell delay = 2.180 ns ( 73.60 % )
            Info: Total interconnect delay = 0.782 ns ( 26.40 % )
        Info: - Longest clock path from clock "clk" to source register is 2.962 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 44; CLK Node = 'clk'
            Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X33_Y14_N5; Fanout = 4; REG Node = 'counter[4]'
            Info: Total cell delay = 2.180 ns ( 73.60 % )
            Info: Total interconnect delay = 0.782 ns ( 26.40 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "speaker" through register "speaker~reg0" is 7.602 ns
    Info: + Longest clock path from clock "clk" to source register is 2.962 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 44; CLK Node = 'clk'
        Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X31_Y13_N3; Fanout = 2; REG Node = 'speaker~reg0'
        Info: Total cell delay = 2.180 ns ( 73.60 % )
        Info: Total interconnect delay = 0.782 ns ( 26.40 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.416 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y13_N3; Fanout = 2; REG Node = 'speaker~reg0'
        Info: 2: + IC(2.292 ns) + CELL(2.124 ns) = 4.416 ns; Loc. = PIN_138; Fanout = 0; PIN Node = 'speaker'
        Info: Total cell delay = 2.124 ns ( 48.10 % )
        Info: Total interconnect delay = 2.292 ns ( 51.90 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Jan 18 19:58:03 2008
    Info: Elapsed time: 00:00:01