dds.tan.rpt

实现任意小数分频的VHDL源代码,我自己写的,仿真结果是正确的,希望对大家有用!我是打算将400M的时钟分为57.344M

Classic Timing Analyzer report for DDS
Wed Jan 16 17:39:02 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'inclk'
  6. tsu
  7. tco
  8. th
  9. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                              ;
+------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                                                                                             ; To                                                                                               ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 6.783 ns                         ; fcw[1]                                                                                           ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[15] ; --         ; inclk    ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 10.542 ns                        ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[15] ; outclk                                                                                           ; inclk      ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; -3.235 ns                        ; fcw[13]                                                                                          ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[13] ; --         ; inclk    ; 0            ;
; Clock Setup: 'inclk'         ; N/A   ; None          ; 311.43 MHz ( period = 3.211 ns ) ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[0]  ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[15] ; inclk      ; inclk    ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                                  ;                                                                                                  ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+