dds.tan.rpt

来自「实现任意小数分频的VHDL源代码,我自己写的,仿真结果是正确的,希望对大家有用!」· RPT 代码 · 共 262 行 · 第 1/5 页

; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C20F484C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; inclk           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'inclk'                                                                                                                                                                                                                                                                                                                                                     ;
+-------+------------------------------------------------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                             ; To                                                                                               ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 311.43 MHz ( period = 3.211 ns )               ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[0]  ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[15] ; inclk      ; inclk    ; None                        ; None                      ; 2.947 ns                ;
; N/A   ; 319.08 MHz ( period = 3.134 ns )               ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[1]  ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[15] ; inclk      ; inclk    ; None                        ; None                      ; 2.870 ns                ;
; N/A   ; 320.00 MHz ( period = 3.125 ns )               ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[0]  ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[14] ; inclk      ; inclk    ; None                        ; None                      ; 2.861 ns                ;
; N/A   ; 327.98 MHz ( period = 3.049 ns )               ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[2]  ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[15] ; inclk      ; inclk    ; None                        ; None                      ; 2.785 ns                ;
; N/A   ; 328.08 MHz ( period = 3.048 ns )               ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[1]  ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[14] ; inclk      ; inclk    ; None                        ; None                      ; 2.784 ns                ;
; N/A   ; 329.06 MHz ( period = 3.039 ns )               ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[0]  ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[13] ; inclk      ; inclk    ; None                        ; None                      ; 2.775 ns                ;
; N/A   ; 331.90 MHz ( period = 3.013 ns )               ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[3]  ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[15] ; inclk      ; inclk    ; None                        ; None                      ; 2.749 ns                ;
; N/A   ; 337.50 MHz ( period = 2.963 ns )               ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[2]  ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[14] ; inclk      ; inclk    ; None                        ; None                      ; 2.699 ns                ;
; N/A   ; 337.61 MHz ( period = 2.962 ns )               ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[1]  ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[13] ; inclk      ; inclk    ; None                        ; None                      ; 2.698 ns                ;
; N/A   ; 338.64 MHz ( period = 2.953 ns )               ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[0]  ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[12] ; inclk      ; inclk    ; None                        ; None                      ; 2.689 ns                ;
; N/A   ; 341.65 MHz ( period = 2.927 ns )               ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[3]  ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[14] ; inclk      ; inclk    ; None                        ; None                      ; 2.663 ns                ;
; N/A   ; 347.46 MHz ( period = 2.878 ns )               ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[4]  ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[15] ; inclk      ; inclk    ; None                        ; None                      ; 2.614 ns                ;
; N/A   ; 347.58 MHz ( period = 2.877 ns )               ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[2]  ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[13] ; inclk      ; inclk    ; None                        ; None                      ; 2.613 ns                ;
; N/A   ; 347.71 MHz ( period = 2.876 ns )               ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[1]  ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[12] ; inclk      ; inclk    ; None                        ; None                      ; 2.612 ns                ;
; N/A   ; 348.80 MHz ( period = 2.867 ns )               ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[0]  ; lpm_add_sub2:inst|lpm_add_sub:lpm_add_sub_component|add_sub_9mh:auto_generated|pipeline_dffe[11] ; inclk      ; inclk    ; None                        ; None                      ; 2.603 ns                ;