sum_control.hier_info

采用Verilog HDL语言编写的步进电机位置系统

|sum_control
Reset => step_counter~48.OUTPUTSELECT
Reset => step_counter~49.OUTPUTSELECT
Reset => step_counter~50.OUTPUTSELECT
Reset => step_counter~51.OUTPUTSELECT
Reset => step_counter~52.OUTPUTSELECT
Reset => step_counter~53.OUTPUTSELECT
Reset => step_counter~54.OUTPUTSELECT
Reset => step_counter~55.OUTPUTSELECT
Reset => step_counter~56.OUTPUTSELECT
Reset => step_counter~57.OUTPUTSELECT
Reset => step_counter~58.OUTPUTSELECT
Reset => step_counter~59.OUTPUTSELECT
Reset => step_counter~60.OUTPUTSELECT
Reset => step_counter~61.OUTPUTSELECT
Reset => step_counter~62.OUTPUTSELECT
Reset => step_counter~63.OUTPUTSELECT
Reset => step_counter~64.OUTPUTSELECT
Reset => step_counter~65.OUTPUTSELECT
Reset => step_counter~66.OUTPUTSELECT
Reset => step_counter~67.OUTPUTSELECT
Reset => step_counter~68.OUTPUTSELECT
Reset => step_counter~69.OUTPUTSELECT
Reset => step_counter~70.OUTPUTSELECT
Reset => step_counter~71.OUTPUTSELECT
Reset => out_control~2.OUTPUTSELECT
pulse_sum_in => step_counter[22].CLK
pulse_sum_in => step_counter[21].CLK
pulse_sum_in => step_counter[20].CLK
pulse_sum_in => step_counter[19].CLK
pulse_sum_in => step_counter[18].CLK
pulse_sum_in => step_counter[17].CLK
pulse_sum_in => step_counter[16].CLK
pulse_sum_in => step_counter[15].CLK
pulse_sum_in => step_counter[14].CLK
pulse_sum_in => step_counter[13].CLK
pulse_sum_in => step_counter[12].CLK
pulse_sum_in => step_counter[11].CLK
pulse_sum_in => step_counter[10].CLK
pulse_sum_in => step_counter[9].CLK
pulse_sum_in => step_counter[8].CLK
pulse_sum_in => step_counter[7].CLK
pulse_sum_in => step_counter[6].CLK
pulse_sum_in => step_counter[5].CLK
pulse_sum_in => step_counter[4].CLK
pulse_sum_in => step_counter[3].CLK
pulse_sum_in => step_counter[2].CLK
pulse_sum_in => step_counter[1].CLK
pulse_sum_in => step_counter[0].CLK
pulse_sum_in => out_control.CLK
pulse_sum_in => wave_out~0.IN0
pulse_sum_in => step_counter[23].CLK
step_sum[0] => add~0.IN2
step_sum[1] => ~NO_FANOUT~
step_sum[2] => always0~2.IN0
step_sum[3] => always0~3.IN0
step_sum[4] => always0~4.IN0
step_sum[5] => always0~5.IN0
step_sum[6] => always0~6.IN0
step_sum[7] => always0~7.IN0
step_sum[8] => always0~8.IN0
step_sum[9] => always0~9.IN0
step_sum[10] => always0~10.IN0
step_sum[11] => always0~11.IN0
step_sum[12] => always0~12.IN0
step_sum[13] => always0~13.IN0
step_sum[14] => always0~14.IN0
step_sum[15] => always0~15.IN0
step_sum[16] => always0~16.IN0
step_sum[17] => always0~17.IN0
step_sum[18] => always0~18.IN0
step_sum[19] => always0~19.IN0
step_sum[20] => always0~20.IN0
step_sum[21] => always0~21.IN0
step_sum[22] => always0~22.IN0
step_sum[23] => always0~23.IN0
wave_out <= wave_out~0.DB_MAX_OUTPUT_PORT_TYPE