second_pulse_latch.map.summary

采用Verilog HDL语言编写的步进电机位置系统

Flow Status : Successful - Wed Jul 19 23:02:06 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : second_pulse_latch
Top-level Entity Name : second_pulse_latch
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 93
Total pins : 51