wb_cyclone_cpu68.vhd

SoC-Wishbone System IP核的VHDL语言源代码

	signal	ram_dat :				std_logic_vector(LPM_WIDTH-1 downto 0);
	signal	ram_ben :				std_logic_vector((LPM_WIDTH/8)-1 downto 0);
	signal	ram_wen :				std_logic;		-- ram Write Enable
	signal	ram_csn :				std_logic;		-- ram Chip Select
	signal	ram_oen :				std_logic;		-- ram Output Enable

	--	External PIO H/W Interface
	signal	PORT0_IO :			std_logic_vector(7 downto 0);
	signal	PORT1_IO :			std_logic_vector(7 downto 0);
--	signal	PORT2_IO :			std_logic_vector(7 downto 0);
--	signal	PORT3_IO :			std_logic_vector(7 downto 0)

	-- External UART H/W Interface
	signal	iTxD :					std_logic;		-- Tx Data
	signal	iRxD :					std_logic;		-- Rx Data
	signal	uart_irq :			std_logic;		-- UART Interrupt

	signal	SysClk :				std_logic;		-- System Clock
	signal	BrdClk :				std_logic;		-- Board Clock
	signal	nReset :				std_logic;		-- System Reset

	-- *** Temp ***
	signal	RTSn :					std_logic;		-- Request To Send
	signal	CTSn :					std_logic;		-- Clear To Send

begin

-----------------------------------------------------------------------------
-- Connect the Components
-----------------------------------------------------------------------------

cpu : wb_cpu01  port map (
	  DAT_I		=> DAT_I,
	  DAT_O		=> DAT_O,
		SEL_O		=> SEL_O,
		ADR_O		=> ADR_O,
		WE_O		=> WE_O,
		STB_O		=> STB_O,
		CYC_O		=> CYC_O,
		ACK_I		=> ACK_I,
		CLK_I		=> CLK_I,
		RST_I		=> RST_I,
		HALT_I	=> HALT_I,
		IRQ_ICF	=> IRQ_ICF,
		IRQ_OCF	=> IRQ_OCF,
		IRQ_TOF	=> IRQ_TOF,
		IRQ_SCI	=> IRQ_SCI,
		IRQ_I		=> IRQ_I,
		NMI_I		=> NMI_I
  );

rom : wb_lpm_rom
	generic map (
		LPM_WIDTH		=> LPM_WIDTH,
		LPM_WIDTHAD	=> LPM_ROM_WIDTHAD,
		LPM_FILE		=> LPM_FILE,
    LPM_FAMILY	=> LPM_FAMILY
	)
	port map (
	  DAT_O			=> DAT_O_ROM,
		ADR_I			=> ADR_O(LPM_ROM_WIDTHAD-1 downto 0),
		SEL_I			=> SEL_O,
		STB_I			=> STB_O,
		CYC_I			=> rom_sel,
		ACK_O			=> rom_ack,
		CLK_I			=> CLK_I,
		RST_I			=> RST_I
	);

bram : wb_lpm_ram
	generic map (
		LPM_WIDTH		=> LPM_WIDTH,
		LPM_WIDTHAD	=> LPM_BSCTRAM_WIDTHAD,
    LPM_FAMILY	=> LPM_FAMILY
	)
	port map (
	  DAT_I			=> DAT_O,
	  DAT_O			=> DAT_O_BSCTRAM,
		ADR_I			=> ADR_O(LPM_BSCTRAM_WIDTHAD-1 downto 0),
		WE_I			=> WE_O,
		SEL_I			=> SEL_O,
		STB_I			=> STB_O,
		CYC_I			=> bram_sel,
		ACK_O			=> bram_ack,
		CLK_I			=> CLK_I,
		RST_I			=> RST_I
	);

dram : wb_ram
	generic map (
		RAM_WIDTH		=> LPM_WIDTH,
		RAM_WIDTHAD	=> LPM_DSCTRAM_WIDTHAD
	)
	port map (
	  DAT_I			=> DAT_O,
	  DAT_O			=> DAT_O_DSCTRAM,
		ADR_I			=> ADR_O(LPM_DSCTRAM_WIDTHAD-1 downto 0),
		WE_I			=> WE_O,
		SEL_I			=> SEL_O,
		STB_I			=> STB_O,
		CYC_I			=> dram_sel,
		ACK_O			=> dram_ack,
		CLK_I			=> CLK_I,
		RST_I			=> RST_I,
		ram_adr		=> ram_adr,
	  ram_dat		=> ram_dat,
	  ram_ben		=> ram_ben,
	  ram_csn		=> ram_csn,
	  ram_wen		=> ram_wen,
	  ram_oen		=> ram_oen
	);

pio0 : wb_ioport
	port map (
	  DAT_I			=> DAT_O,
	  DAT_O			=> DAT_O_PIO,
		ADR_I			=> ADR_O(2 downto 0),
		WE_I			=> WE_O,
		SEL_I			=> SEL_O(0),
		STB_I			=> STB_O,
		CYC_I			=> pio_sel,
		ACK_O			=> pio_ack,
		CLK_I			=> CLK_I,
		RST_I			=> RST_I,
		PORT0_IO	=> PORT0_IO,
		PORT1_IO	=> PORT1_IO,
		PORT2_IO	=> PORT2_IO,
		PORT3_IO	=> PORT3_IO
	);

uart0 : wb_acia
	port map (
	  DAT_I			=> DAT_O,
	  DAT_O			=> DAT_O_UART,
		ADR_I			=> ADR_O(0),
		WE_I			=> WE_O,
		SEL_I			=> SEL_O(0),
		STB_I			=> STB_O,
		CYC_I			=> uart_sel,
		ACK_O			=> uart_ack,
		CLK_I			=> CLK_I,
		RST_I			=> RST_I,
		IRQ_O			=> uart_irq,
	  TxD				=> iTxD,
		RxD				=> iRxD,
	  RTSn			=> RTSn,
	  CTSn			=> CTSn
	);

-----------------------------------------------------------------------------
-- Concurrent Interconnects
-----------------------------------------------------------------------------
	-- merge te ACKs
	ACK_I		<= rom_ack or dram_ack or bram_ack or pio_ack or uart_ack or dmy_ack;

	IRQ_ICF	<= '0';
	IRQ_OCF	<= '0';
	IRQ_TOF	<= '0';
	IRQ_SCI	<= '0';

	HALT_I	<= '0';
	NMI_I		<= '0';

	IRQ_I		<= uart_irq;		-- connect the UART/ACIA
	CLK_I 	<= SysClk;			-- Connect the CLOCK

-- ******************************************
-- Temporary assignments for DevKit
-- ******************************************
	-- Cyclone DevKit has 32bit SRAM. So we start with FSE_A(2)
	FSE_A(FSE_A'HIGH downto ram_adr'LENGTH+2)		<= (others => '0');
	FSE_A(ram_adr'HIGH+2 downto ram_adr'LOW+2)	<= ram_adr;

	FSE_D(FSE_D'HIGH downto ram_dat'LENGTH)	<= (others => 'Z');
	FSE_D(ram_dat'RANGE)	<= ram_dat;

	SRAM_BE_N(3 downto 1)	<= (others => '1');
	SRAM_BE_N(0)	<= ram_ben(0);
	SRAM_CS_N			<= ram_csn;
	SRAM_OE_N			<= ram_oen;
	SRAM_WE_N			<= ram_wen;

	BrdClk				<= PLD_CLOCKINPUT(1);
	nReset				<= PLD_CLEAR_N;

	Display_7_Segment(15 downto 8)	<= PORT0_IO;
	Display_7_Segment( 7 downto 0)	<= PORT1_IO;

	PROTO2_IO(39)	<= SysClk;

	ENET_BE_N			<= (others => '1');
	ENET_ADS_N		<= '1';
	ENET_AEN			<= '1';
	ENET_CYCLE_N	<= '1';
	ENET_DATACS_N	<= '1';
	ENET_IOR_N		<= '1';
	ENET_IOW_N		<= '1';
	ENET_LDEV_N		<= '1';
	ENET_W_R_N		<= '1';

	FLASH_CS_N		<= '1';
	FLASH_OE_N		<= '1';
	FLASH_RW_N		<= '1';

	TXD(1)				<= iTxD;
	iRxD					<= RXD(1);

	TXD(2)				<= '1';

	DTR						<= (others => '1');
	RTS						<= (others => '1');
	CTSn					<= '0';
-- ******************************************

-----------------------------------------------------------------------------
-- Memory Map Decoding
-----------------------------------------------------------------------------
-- memory decoding
dcdr : process(ADR_O, CYC_O, STB_O, DAT_O_ROM, DAT_O_BSCTRAM, DAT_O_DSCTRAM, DAT_O_PIO, DAT_O_UART)
	begin
		-- assume all are negated
		rom_sel		<= '0';
		dram_sel	<= '0';
		bram_sel	<= '0';
		pio_sel		<= '0';
		uart_sel	<= '0';
		dmy_ack		<= '0';
		DAT_I			<= (others => '0');

		-- ROM
		if ADR_O(ADR_O'HIGH) = '1' then
			rom_sel	<= CYC_O and STB_O;
			DAT_I	<= DAT_O_ROM;
		else
			-- see if SHORT Mem or I/O selected
			if ADR_O(ADR_O'HIGH-1 downto 8) = "0000000" then

				if ADR_O(7) = '1' then
					-- Short Memory BSCT RAM $00FF - $0080
					bram_sel	<= CYC_O;
					DAT_I	<= DAT_O_BSCTRAM;
				else
					-- Short I/O = $007F - $0000 (4 byte blocks)
					case ADR_O(6 downto 2) is

						when "00000" | "00001" =>	-- $0007 - $0000
						-- PIO
							pio_sel	<= CYC_O and STB_O;
							DAT_I	<= DAT_O_PIO;

						when "00100" =>	-- $0013 - $0010
						-- UART
							uart_sel	<= CYC_O and STB_O;
							DAT_I	<= DAT_O_UART;

						when others =>
							dmy_ack	<= CYC_O and STB_O;
							DAT_I	<= X"A5";

					end case;
				end if;
			else
				-- DSCT RAM $7FFF - $0100
				dram_sel	<= CYC_O and STB_O;
				DAT_I	<= DAT_O_DSCTRAM;

			end if;
		end if;
	end process;

-----------------------------------------------------------------------------
-- System Clock (4.9152MHz) generator
-----------------------------------------------------------------------------
clkgen : process( BrdClk )
	constant	SYSTEM_CLK :	integer := 4915;	-- in KHz
	constant	DIVISOR :			integer := (BRD_CLOCK / SYSTEM_CLK) / 2;
	variable	clkcntr :			integer range 0 to DIVISOR-1;
	begin
		if BrdClk'EVENT and BrdClk = '1' then
			if nReset = '0' then
				SysClk	<= '0';
				clkcntr	:= 0;
			else
				if clkcntr = DIVISOR-1 then
					clkcntr	:= 0;
					SysClk	<= not( SysClk );	-- toggle the system clock
				else
					clkcntr	:= clkcntr + 1;
				end if;
			end if;
		end if;
	end process;

-----------------------------------------------------------------------------
-- System System RESET
-----------------------------------------------------------------------------
rstgen : process( SysClk )
	constant	RESETDLY :		integer := 32;
	variable	rstcntr :			integer range 0 to RESETDLY-1;
	variable	rst :					std_logic;
	begin
		if nReset = '0' then
			rst			:= '0';
			rstcntr	:= 0;
		elsif SysClk'EVENT and SysClk = '1' then
			if rstcntr = RESETDLY - 1 then
				rst			:= '1';
			else
				rst			:= '0';
				rstcntr	:= rstcntr + 1;
			end if;
		end if;
		RST_I		<= not( rst );
	end process;

end bhv_wb_cyclone_cpu68; --===================== End of architecture =======================--