ufm.v

Altera epm240 的ufm调用。

	initial
		dffe11a[7:7] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (wire_dffe11a_ENA[7:7] == 1'b1)   dffe11a[7:7] <= wire_dffe11a_D[7:7];
	assign
		wire_dffe11a_D = {sipo_q[15:8]};
	assign
		wire_dffe11a_ENA = {8{(dffe7 & (~ tmp_decode))}};
	// synopsys translate_off
	initial
		dffe12 = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		  dffe12 <= busy_arclk;
	// synopsys translate_off
	initial
		dffe13 = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		  dffe13 <= busy_drclk;
	// synopsys translate_off
	initial
		dffe2 = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		  dffe2 <= start_decode;
	// synopsys translate_off
	initial
		dffe3 = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		  dffe3 <= dffe2;
	// synopsys translate_off
	initial
		dffe4 = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (start_op == 1'b1)   dffe4 <= mux_nread;
	// synopsys translate_off
	initial
		dffe5 = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		  dffe5 <= copy_tmp_decode;
	// synopsys translate_off
	initial
		dffe7 = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (data_valid_en == 1'b1)   dffe7 <= tmp_data_valid2;
	// synopsys translate_off
	initial
		dffe8 = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		  dffe8 <= (dffe7 & (~ tmp_decode));
	// synopsys translate_off
	initial
		dffe9a[0:0] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (add_en == 1'b1)   dffe9a[0:0] <= wire_dffe9a_D[0:0];
	// synopsys translate_off
	initial
		dffe9a[1:1] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (add_en == 1'b1)   dffe9a[1:1] <= wire_dffe9a_D[1:1];
	// synopsys translate_off
	initial
		dffe9a[2:2] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (add_en == 1'b1)   dffe9a[2:2] <= wire_dffe9a_D[2:2];
	// synopsys translate_off
	initial
		dffe9a[3:3] = 0;
	// synopsys translate_on
	always @ ( posedge ufm_osc)
		if (add_en == 1'b1)   dffe9a[3:3] <= wire_dffe9a_D[3:3];
	assign
		wire_dffe9a_D = {Z_var};
	// synopsys translate_off
	initial
		wire_cntr6_q_int = 0;
	// synopsys translate_on
	always @(posedge wire_cntr6_clock)
			if ( wire_cntr6_clk_en == 1'b1)
					if (wire_cntr6_q_int[4:0] == 5'd27)
						wire_cntr6_q_int <= 5'b0;
					else
						wire_cntr6_q_int <= wire_cntr6_q_int[4:0] + 1'b1;
	assign
		wire_cntr6_q = wire_cntr6_q_int[4:0];
	assign
		wire_cntr6_clk_en = tmp_decode,
		wire_cntr6_clock = ufm_osc;
	maxii_ufm   maxii_ufm_block1
	( 
	.arclk(ufm_arclk),
	.ardin(ufm_ardin),
	.arshft(ufm_arshft),
	.bgpbusy(wire_maxii_ufm_block1_bgpbusy),
	.busy(),
	.drclk(ufm_drclk),
	.drdin(ufm_drdin),
	.drdout(wire_maxii_ufm_block1_drdout),
	.drshft(ufm_drshft),
	.osc(wire_maxii_ufm_block1_osc),
	.oscena(ufm_oscena)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_off
	`endif
	,
	.erase(1'b0),
	.program(1'b0)
	`ifdef FORMAL_VERIFICATION
	`else
	// synopsys translate_on
	`endif
	// synopsys translate_off
	,
	.ctrl_bgpbusy(),
	.devclrn(),
	.devpor(),
	.sbdin(),
	.sbdout()
	// synopsys translate_on
	);
	defparam
		maxii_ufm_block1.address_width = 9,
		maxii_ufm_block1.init_file = "text.mif",
		maxii_ufm_block1.mem1 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3FFF,
		maxii_ufm_block1.mem10 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6FFF,
		maxii_ufm_block1.mem11 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF77FF,
		maxii_ufm_block1.mem12 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7CFF,
		maxii_ufm_block1.mem13 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF39FF,
		maxii_ufm_block1.mem14 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5EFF,
		maxii_ufm_block1.mem15 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF79FF,
		maxii_ufm_block1.mem16 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF71FF,
		maxii_ufm_block1.mem2 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF06FF,
		maxii_ufm_block1.mem3 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5BFF,
		maxii_ufm_block1.mem4 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4FFF,
		maxii_ufm_block1.mem5 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF66FF,
		maxii_ufm_block1.mem6 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6DFF,
		maxii_ufm_block1.mem7 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7DFF,
		maxii_ufm_block1.mem8 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF07FF,
		maxii_ufm_block1.mem9 = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FFF,
		maxii_ufm_block1.osc_sim_setting = 180000,
		maxii_ufm_block1.lpm_type = "maxii_ufm";
	assign
		add_en = (tmp_add_en & read_op),
		add_load = (tmp_add_load & read_op),
		arclk = (tmp_arclk0 & read_op),
		busy_arclk = arclk,
		busy_drclk = in_read_drclk,
		control_mux = (((~ q4) & ((q3 | q2) | q1)) | q4),
		copy_tmp_decode = tmp_decode,
		data_valid = dffe8,
		data_valid_en = ((q4 & q3) & q1),
		dly_tmp_decode = dffe5,
		do = dffe11a,
		drdin = 1'b0,
		gated1 = dffe12,
		gated2 = dffe13,
		hold_decode = ((~ dffe3) & real_decode),
		in_read_data_en = (tmp_in_read_data_en & read_op),
		in_read_drclk = (tmp_in_read_drclk & read_op),
		in_read_drshft = (tmp_in_read_drshft & read_op),
		mux_nread = (((~ control_mux) & read) | (control_mux & (~ data_valid_en))),
		nbusy = ((~ dly_tmp_decode) & (~ ufm_bgpbusy)),
		q0 = wire_cntr6_q[0],
		q1 = wire_cntr6_q[1],
		q2 = wire_cntr6_q[2],
		q3 = wire_cntr6_q[3],
		q4 = wire_cntr6_q[4],
		read = (~ nread),
		read_op = tmp_read,
		real_decode = start_decode,
		shiftin = {dffe9a[2:0], 1'b0},
		sipo_q = {dffe10a15[0:0], dffe10a14[0:0], dffe10a13[0:0], dffe10a12[0:0], dffe10a11[0:0], dffe10a10[0:0], dffe10a9[0:0], dffe10a8[0:0], dffe10a7[0:0], dffe10a6[0:0], dffe10a5[0:0], dffe10a4[0:0], dffe10a3[0:0], dffe10a2[0:0], dffe10a1[0:0], dffe10a0[0:0]},
		start_decode = (mux_nread & (~ ufm_bgpbusy)),
		start_op = (hold_decode | stop_op),
		stop_op = ((((q4 & q3) & (~ q2)) & q1) & q0),
		tmp_add_en = ((~ q4) & ((~ q3) | ((~ q2) & (~ q1)))),
		tmp_add_load = (~ ((~ q4) & (((((~ q3) & q2) | ((~ q3) & q0)) | ((~ q3) & q1)) | ((q3 & (~ q2)) & (~ q1))))),
		tmp_arclk = (gated1 & (~ ufm_osc)),
		tmp_arclk0 = ((~ q4) & ((~ q3) | (((~ q2) & (~ q1)) & (~ q0)))),
		tmp_ardin = dffe9a[3],
		tmp_arshft = add_en,
		tmp_data_valid2 = (stop_op & read_op),
		tmp_decode = tmp_read,
		tmp_drclk = (gated2 & (~ ufm_osc)),
		tmp_in_read_data_en = (((~ q4) & ((q3 & q2) | (q3 & q1))) | (q4 & (((~ q3) | ((~ q2) & (~ q1))) | (q1 & (~ q0))))),
		tmp_in_read_drclk = (((~ q4) & ((q3 & q2) | (q3 & q1))) | (q4 & (((~ q3) | ((~ q2) & (~ q1))) | (q1 & (~ q0))))),
		tmp_in_read_drshft = (~ (((((~ q4) & q3) & (~ q2)) & q1) & q0)),
		tmp_read = dffe4,
		ufm_arclk = tmp_arclk,
		ufm_ardin = tmp_ardin,
		ufm_arshft = tmp_arshft,
		ufm_bgpbusy = wire_maxii_ufm_block1_bgpbusy,
		ufm_drclk = tmp_drclk,
		ufm_drdin = drdin,
		ufm_drdout = wire_maxii_ufm_block1_drdout,
		ufm_drshft = in_read_drshft,
		ufm_osc = wire_maxii_ufm_block1_osc,
		ufm_oscena = 1'b1,
		X_var = (shiftin & {4{(~ add_load)}}),
		Y_var = (addr & {4{add_load}}),
		Z_var = (X_var | Y_var);
endmodule //UFM_altufm_parallel_nqi
//VALID FILE


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module UFM (
	nread,
	addr,
	nbusy,
	data_valid,
	do)/* synthesis synthesis_clearbox = 1 */;

	input	  nread;
	input	[3:0]  addr;
	output	  nbusy;
	output	  data_valid;
	output	[7:0]  do;

	wire [7:0] sub_wire0;
	wire  sub_wire1;
	wire  sub_wire2;
	wire [7:0] do = sub_wire0[7:0];
	wire  data_valid = sub_wire1;
	wire  nbusy = sub_wire2;

	UFM_altufm_parallel_nqi	UFM_altufm_parallel_nqi_component (
				.addr (addr),
				.nread (nread),
				.do (sub_wire0),
				.data_valid (sub_wire1),
				.nbusy (sub_wire2));

endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: WIZMAN_OVERRIDE_CBX_GEN_MODE STRING "ON"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: PRIVATE: INTENDED_DEVICE_PART STRING ""
// Retrieval info: PRIVATE: INTERFACE_CHOICE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: ACCESS_MODE STRING "READ_ONLY"
// Retrieval info: CONSTANT: WIDTH_ADDRESS NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_DATA NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_UFM_ADDRESS NUMERIC "9"
// Retrieval info: CONSTANT: LPM_FILE STRING "text.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX II"
// Retrieval info: CONSTANT: OSC_FREQUENCY NUMERIC "180000"
// Retrieval info: USED_PORT: nread 0 0 0 0 INPUT NODEFVAL nread
// Retrieval info: USED_PORT: addr 0 0 4 0 INPUT NODEFVAL addr[3..0]
// Retrieval info: USED_PORT: nbusy 0 0 0 0 OUTPUT NODEFVAL nbusy
// Retrieval info: USED_PORT: data_valid 0 0 0 0 OUTPUT NODEFVAL data_valid
// Retrieval info: USED_PORT: do 0 0 8 0 OUTPUT NODEFVAL do[7..0]
// Retrieval info: CONNECT: @nread 0 0 0 0 nread 0 0 0 0
// Retrieval info: CONNECT: @addr 0 0 4 0 addr 0 0 4 0
// Retrieval info: CONNECT: nbusy 0 0 0 0 @nbusy 0 0 0 0
// Retrieval info: CONNECT: data_valid 0 0 0 0 @data_valid 0 0 0 0
// Retrieval info: CONNECT: do 0 0 8 0 @do 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ufm.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ufm.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ufm.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ufm.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ufm_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ufm_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL UFM_bb.v TRUE