main.v

来自「Altera epm240 的ufm调用。」· Verilog 代码 · 共 56 行

//main.v

module	MAIN(
				ds_, ps_, csRam_,
				clkOSC, clkDSP, reset_, sel,
				segment, dig, dv, clkOut
			);
			
	input	ds_;
	input	ps_;
	output	csRam_;
	
	input	clkOSC;
	input	clkDSP;
	input	reset_;
	input	sel;
	
	output	[7:0]segment;
	output	dig;
	output	dv;
	
	reg		[24:0]timer;
	output	clkOut;
	
	wire	[3:0]addr;
	
	wire	read_;
	wire	busy_;
	wire	clk;
	
	assign	csRam_ = ds_ & ps_;
	assign	addr = timer[24:21];
	assign	dig = 1'b1;
	assign	read_ = ~busy_;
	assign	clkOut= timer[24];
	assign	clk = sel ? clkOSC : clkDSP;
	
	always @(posedge clk or negedge reset_) begin
		if(reset_ == 1'b0) begin
			timer <= 25'b0;
		end
		else begin
			timer <= timer + 1'b1;
		end
	end
	
	UFM ufm(
				.nread(read_),
				.addr(addr),
				.nbusy(busy_),
				.data_valid(dv),
				.do(segment)
			);
		
		
endmodule