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📄 main.fit.eqn

📁 Altera epm240 的ufm调用。
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

--A1L6 is csRam_~0 at LC_X2_Y4_N0
--operation mode is normal

A1L6 = ps_ & ds_;


--C1_dffe11a[0] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe11a[0] at LC_X5_Y4_N0
--operation mode is normal

C1_dffe11a[0]_lut_out = GND;
C1_dffe11a[0] = DFFEAS(C1_dffe11a[0]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1_wire_dffe11a_ENA[7], C1_dffe10a8[0], , , VCC);


--C1_dffe11a[1] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe11a[1] at LC_X5_Y4_N6
--operation mode is normal

C1_dffe11a[1]_lut_out = C1_dffe10a9[0];
C1_dffe11a[1] = DFFEAS(C1_dffe11a[1]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1_wire_dffe11a_ENA[7], , , , );


--C1_dffe11a[2] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe11a[2] at LC_X3_Y4_N1
--operation mode is normal

C1_dffe11a[2]_lut_out = GND;
C1_dffe11a[2] = DFFEAS(C1_dffe11a[2]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1_wire_dffe11a_ENA[7], C1_dffe10a10[0], , , VCC);


--C1_dffe11a[3] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe11a[3] at LC_X3_Y4_N7
--operation mode is normal

C1_dffe11a[3]_lut_out = C1_dffe10a11[0];
C1_dffe11a[3] = DFFEAS(C1_dffe11a[3]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1_wire_dffe11a_ENA[7], , , , );


--C1_dffe11a[4] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe11a[4] at LC_X3_Y4_N3
--operation mode is normal

C1_dffe11a[4]_lut_out = GND;
C1_dffe11a[4] = DFFEAS(C1_dffe11a[4]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1_wire_dffe11a_ENA[7], C1_dffe10a12[0], , , VCC);


--C1_dffe11a[5] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe11a[5] at LC_X3_Y4_N2
--operation mode is normal

C1_dffe11a[5]_lut_out = GND;
C1_dffe11a[5] = DFFEAS(C1_dffe11a[5]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1_wire_dffe11a_ENA[7], C1_dffe10a13[0], , , VCC);


--C1_dffe11a[6] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe11a[6] at LC_X5_Y4_N5
--operation mode is normal

C1_dffe11a[6]_lut_out = GND;
C1_dffe11a[6] = DFFEAS(C1_dffe11a[6]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1_wire_dffe11a_ENA[7], C1_dffe10a14[0], , , VCC);


--C1_dffe11a[7] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe11a[7] at LC_X5_Y4_N2
--operation mode is normal

C1_dffe11a[7]_lut_out = C1_dffe10a15[0];
C1_dffe11a[7] = DFFEAS(C1_dffe11a[7]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1_wire_dffe11a_ENA[7], , , , );


--timer[24] is timer[24] at LC_X4_Y3_N7
--operation mode is normal

timer[24]_carry_eqn = (!A1L38 & A1L88) # (A1L38 & A1L98);
timer[24]_lut_out = timer[24] $ !timer[24]_carry_eqn;
timer[24] = DFFEAS(timer[24]_lut_out, GLOBAL(A1L4), GLOBAL(reset_), , , , , , );


--C1_ufm_drclk is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|ufm_drclk at LC_X2_Y1_N2
--operation mode is normal

C1_dffe13_qfbk = C1_dffe13;
C1_ufm_drclk = !C1_wire_maxii_ufm_block1_osc & C1_dffe13_qfbk;

--C1_dffe13 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe13 at LC_X2_Y1_N2
--operation mode is normal

C1_dffe13 = DFFEAS(C1_ufm_drclk, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , , C1L27, , , VCC);


--C1_dffe4 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe4 at LC_X4_Y2_N6
--operation mode is normal

C1_dffe4_lut_out = C1L77 & !C1_wire_maxii_ufm_block1_bgpbusy & !C1_dffe5 # !C1L77 & (!C1_data_valid_en);
C1_dffe4 = DFFEAS(C1_dffe4_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1_start_op, , , , );


--C1_wire_cntr6_q_int[4] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|wire_cntr6_q_int[4] at LC_X4_Y1_N6
--operation mode is normal

C1_wire_cntr6_q_int[4]_lut_out = C1L3 $ (C1_wire_cntr6_q_int[4] & C1L08);
C1_wire_cntr6_q_int[4] = DFFEAS(C1_wire_cntr6_q_int[4]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1_dffe4, , , , );


--C1_wire_cntr6_q_int[3] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|wire_cntr6_q_int[3] at LC_X4_Y1_N2
--operation mode is normal

C1_wire_cntr6_q_int[3]_lut_out = C1L7 $ (C1_wire_cntr6_q_int[4] & C1L08);
C1_wire_cntr6_q_int[3] = DFFEAS(C1_wire_cntr6_q_int[3]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1_dffe4, , , , );


--C1_wire_cntr6_q_int[2] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|wire_cntr6_q_int[2] at LC_X4_Y1_N9
--operation mode is normal

C1_wire_cntr6_q_int[2]_lut_out = C1L31 $ (C1L08 & C1_wire_cntr6_q_int[4]);
C1_wire_cntr6_q_int[2] = DFFEAS(C1_wire_cntr6_q_int[2]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1_dffe4, , , , );


--C1L08 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|tmp_data_valid2~21 at LC_X4_Y1_N8
--operation mode is normal

C1_wire_cntr6_q_int[1]_qfbk = C1_wire_cntr6_q_int[1];
C1L08 = C1_wire_cntr6_q_int[3] & !C1_wire_cntr6_q_int[2] & C1_wire_cntr6_q_int[1]_qfbk & C1_wire_cntr6_q_int[0];

--C1_wire_cntr6_q_int[1] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|wire_cntr6_q_int[1] at LC_X4_Y1_N8
--operation mode is normal

C1_wire_cntr6_q_int[1] = DFFEAS(C1L08, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1_dffe4, C1L4, , , VCC);


--C1L58 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|ufm_drshft~20 at LC_X4_Y2_N5
--operation mode is normal

C1L58 = C1_dffe4 & (C1_wire_cntr6_q_int[4] # !C1L08);


--C1_dffe9a[3] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe9a[3] at LC_X4_Y4_N2
--operation mode is normal

C1_dffe9a[3]_lut_out = C1_dffe4 & (C1L2 & (timer[24]) # !C1L2 & C1_dffe9a[2]) # !C1_dffe4 & (C1_dffe9a[2]);
C1_dffe9a[3] = DFFEAS(C1_dffe9a[3]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1_ufm_arshft, , , , );


--C1_dffe12 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe12 at LC_X3_Y1_N4
--operation mode is normal

C1_dffe12_lut_out = C1L38 & (!C1_wire_cntr6_q_int[0] & C1L09 # !C1_wire_cntr6_q_int[3]);
C1_dffe12 = DFFEAS(C1_dffe12_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , , , , , );


--C1_ufm_arclk is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|ufm_arclk at LC_X3_Y1_N2
--operation mode is normal

C1_ufm_arclk = C1_dffe12 & (!C1_wire_maxii_ufm_block1_osc);


--C1L38 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|ufm_arshft~26 at LC_X4_Y1_N4
--operation mode is normal

C1L38 = C1_dffe4 & (!C1_wire_cntr6_q_int[4]);


--C1L1 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|add_load~87 at LC_X4_Y2_N8
--operation mode is normal

C1L1 = C1_wire_cntr6_q_int[3] & (C1_wire_cntr6_q_int[1] # C1_wire_cntr6_q_int[2]);


--C1_dffe10a8[0] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe10a8[0] at LC_X3_Y2_N7
--operation mode is normal

C1_dffe10a8[0]_lut_out = GND;
C1_dffe10a8[0] = DFFEAS(C1_dffe10a8[0]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1L27, C1_dffe10a7[0], , , VCC);


--C1_dffe7 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe7 at LC_X4_Y1_N3
--operation mode is normal

C1_dffe7_lut_out = C1L08 & (C1_dffe4 & C1_wire_cntr6_q_int[4]);
C1_dffe7 = DFFEAS(C1_dffe7_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1_data_valid_en, , , , );


--C1_wire_dffe11a_ENA[7] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|wire_dffe11a_ENA[7] at LC_X4_Y4_N8
--operation mode is normal

C1_wire_dffe11a_ENA[7] = !C1_dffe4 & (C1_dffe7);

--C1_dffe8 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe8 at LC_X4_Y4_N8
--operation mode is normal

C1_dffe8 = DFFEAS(C1_wire_dffe11a_ENA[7], GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , , , , , );


--C1_dffe10a9[0] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe10a9[0] at LC_X3_Y2_N3
--operation mode is normal

C1_dffe10a9[0]_lut_out = GND;
C1_dffe10a9[0] = DFFEAS(C1_dffe10a9[0]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1L27, C1_dffe10a8[0], , , VCC);


--C1_dffe10a10[0] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe10a10[0] at LC_X3_Y4_N0
--operation mode is normal

C1_dffe10a10[0]_lut_out = GND;
C1_dffe10a10[0] = DFFEAS(C1_dffe10a10[0]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1L27, C1_dffe10a9[0], , , VCC);


--C1_dffe10a11[0] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe10a11[0] at LC_X3_Y4_N8
--operation mode is normal

C1_dffe10a11[0]_lut_out = GND;
C1_dffe10a11[0] = DFFEAS(C1_dffe10a11[0]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1L27, C1_dffe10a10[0], , , VCC);


--C1_dffe10a12[0] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe10a12[0] at LC_X3_Y4_N5
--operation mode is normal

C1_dffe10a12[0]_lut_out = C1_dffe10a11[0];
C1_dffe10a12[0] = DFFEAS(C1_dffe10a12[0]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1L27, , , , );


--C1_dffe10a13[0] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe10a13[0] at LC_X3_Y4_N6
--operation mode is normal

C1_dffe10a13[0]_lut_out = GND;
C1_dffe10a13[0] = DFFEAS(C1_dffe10a13[0]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1L27, C1_dffe10a12[0], , , VCC);


--C1_dffe10a14[0] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe10a14[0] at LC_X3_Y4_N4
--operation mode is normal

C1_dffe10a14[0]_lut_out = GND;
C1_dffe10a14[0] = DFFEAS(C1_dffe10a14[0]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1L27, C1_dffe10a13[0], , , VCC);


--C1_dffe10a15[0] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe10a15[0] at LC_X3_Y4_N9
--operation mode is normal

C1_dffe10a15[0]_lut_out = GND;
C1_dffe10a15[0] = DFFEAS(C1_dffe10a15[0]_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1L27, C1_dffe10a14[0], , , VCC);


--A1L4 is clk~7 at LC_X5_Y3_N2
--operation mode is normal

A1L4 = sel & (clkOSC) # !sel & clkDSP;


--timer[23] is timer[23] at LC_X4_Y3_N6
--operation mode is arithmetic

timer[23]_carry_eqn = (!A1L38 & A1L58) # (A1L38 & A1L68);
timer[23]_lut_out = timer[23] $ (timer[23]_carry_eqn);
timer[23] = DFFEAS(timer[23]_lut_out, GLOBAL(A1L4), GLOBAL(reset_), , , , , , );

--A1L88 is timer[23]~180 at LC_X4_Y3_N6
--operation mode is arithmetic

A1L88_cout_0 = !A1L58 # !timer[23];
A1L88 = CARRY(A1L88_cout_0);

--A1L98 is timer[23]~180COUT1_294 at LC_X4_Y3_N6
--operation mode is arithmetic

A1L98_cout_1 = !A1L68 # !timer[23];
A1L98 = CARRY(A1L98_cout_1);


--C1L17 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|in_read_drclk~137 at LC_X4_Y1_N1
--operation mode is normal

C1_wire_cntr6_q_int[0]_qfbk = C1_wire_cntr6_q_int[0];
C1L17 = C1_wire_cntr6_q_int[1] & (!C1_wire_cntr6_q_int[0]_qfbk);

--C1_wire_cntr6_q_int[0] is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|wire_cntr6_q_int[0] at LC_X4_Y1_N1
--operation mode is normal

C1_wire_cntr6_q_int[0] = DFFEAS(C1L17, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , C1_dffe4, C1L01, , , VCC);


--C1L27 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|in_read_drclk~138 at LC_X4_Y2_N4
--operation mode is normal

C1L27 = C1_dffe4 & (C1L1 & (C1L17 # !C1_wire_cntr6_q_int[4]) # !C1L1 & C1_wire_cntr6_q_int[4]);


--C1_data_valid_en is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|data_valid_en at LC_X4_Y2_N2
--operation mode is normal

C1_data_valid_en = C1_wire_cntr6_q_int[1] & C1_wire_cntr6_q_int[3] & C1_wire_cntr6_q_int[4];


--C1_dffe5 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe5 at LC_X4_Y2_N7
--operation mode is normal

C1_dffe5_lut_out = GND;
C1_dffe5 = DFFEAS(C1_dffe5_lut_out, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , , C1_dffe4, , , VCC);


--C1L77 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|mux_nread~159 at LC_X4_Y2_N0
--operation mode is normal

C1L77 = !C1_wire_cntr6_q_int[4] & !C1_wire_cntr6_q_int[1] & !C1_wire_cntr6_q_int[3] & !C1_wire_cntr6_q_int[2];


--C1_start_decode is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|start_decode at LC_X4_Y2_N1
--operation mode is normal

C1_start_decode = !C1_wire_maxii_ufm_block1_bgpbusy & (C1L77 & !C1_dffe5 # !C1L77 & (!C1_data_valid_en));

--C1_dffe2 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe2 at LC_X4_Y2_N1
--operation mode is normal

C1_dffe2 = DFFEAS(C1_start_decode, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , , , , , );


--C1_start_op is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|start_op at LC_X4_Y2_N9
--operation mode is normal

C1_dffe3_qfbk = C1_dffe3;
C1_start_op = C1_wire_cntr6_q_int[4] & (C1L08 # C1_start_decode & !C1_dffe3_qfbk) # !C1_wire_cntr6_q_int[4] & C1_start_decode & !C1_dffe3_qfbk;

--C1_dffe3 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|dffe3 at LC_X4_Y2_N9
--operation mode is normal

C1_dffe3 = DFFEAS(C1_start_op, GLOBAL(C1_wire_maxii_ufm_block1_osc), VCC, , , C1_dffe2, , , VCC);


--C1L3 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|add~76 at LC_X3_Y1_N9
--operation mode is normal

C1L3 = C1_wire_cntr6_q_int[4] $ (!C1L8);


--C1L4 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|add~81 at LC_X3_Y1_N6
--operation mode is arithmetic

C1L4 = C1_wire_cntr6_q_int[1] $ C1L11;

--C1L5 is UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|add~83 at LC_X3_Y1_N6
--operation mode is arithmetic

C1L5_cout_0 = !C1L11 # !C1_wire_cntr6_q_int[1];

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