main.map.rpt

Altera epm240 的ufm调用。

; Show Parameter Settings Tables in Synthesis Report                 ; On           ; On            ;
+--------------------------------------------------------------------+--------------+---------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                         ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                     ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------+
; UFM.v                            ; yes             ; User Verilog HDL File  ; D:/My Documents/Project/FPGA/MAX_UFM/0000/UFM.v  ;
; main.v                           ; yes             ; User Verilog HDL File  ; D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v ;
+----------------------------------+-----------------+------------------------+--------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                                        ;
+-----------------------------------+------------------------------------------------------------------------------------------------+
; Resource                          ; Usage                                                                                          ;
+-----------------------------------+------------------------------------------------------------------------------------------------+
; Total logic elements              ; 90                                                                                             ;
; Total combinational functions     ; 59                                                                                             ;
;     -- Total 4-input functions    ; 11                                                                                             ;
;     -- Total 3-input functions    ; 10                                                                                             ;
;     -- Total 2-input functions    ; 7                                                                                              ;
;     -- Total 1-input functions    ; 30                                                                                             ;
;     -- Total 0-input functions    ; 1                                                                                              ;
; Combinational cells for routing   ; 0                                                                                              ;
; Total registers                   ; 66                                                                                             ;
; Total logic cells in carry chains ; 30                                                                                             ;
; I/O pins                          ; 18                                                                                             ;
; UFM blocks                        ; 1                                                                                              ;
; Maximum fan-out node              ; UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component|wire_maxii_ufm_block1_drdout ;
; Maximum fan-out                   ; 44                                                                                             ;
; Total fan-out                     ; 318                                                                                            ;
; Average fan-out                   ; 2.92                                                                                           ;
+-----------------------------------+------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                 ;
+-------------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------+
; Compilation Hierarchy Node                                        ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                     ;
+-------------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------+
; |MAIN                                                             ; 90 (28)     ; 66           ; 1          ; 18   ; 0            ; 24 (3)       ; 31 (0)            ; 35 (25)          ; 30 (25)         ; |MAIN                                                                   ;
;    |UFM:ufm|                                                      ; 62 (0)      ; 41           ; 1          ; 0    ; 0            ; 21 (0)       ; 31 (0)            ; 10 (0)           ; 5 (0)           ; |MAIN|UFM:ufm                                                           ;
;       |UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component| ; 62 (62)     ; 41           ; 1          ; 0    ; 0            ; 21 (21)      ; 31 (31)           ; 10 (10)          ; 5 (5)           ; |MAIN|UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component ;
+-------------------------------------------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 66    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 25    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 35    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/My Documents/Project/FPGA/MAX_UFM/0000/Main.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Wed Jan 02 13:01:11 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MAX_UFM -c Main
Info: Found 2 design units, including 2 entities, in source file UFM.v
    Info: Found entity 1: UFM_altufm_parallel_nqi
    Info: Found entity 2: UFM
Info: Found 1 design units, including 1 entities, in source file main.v
    Info: Found entity 1: MAIN
Info: Elaborating entity "MAIN" for the top level hierarchy
Info: Elaborating entity "UFM" for hierarchy "UFM:ufm"
Info: Elaborating entity "UFM_altufm_parallel_nqi" for hierarchy "UFM:ufm|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component"
Info: (10265) Verilog HDL Module Instantiation information at UFM.v(393): instance "maxii_ufm_block1" connects port "busy" to an empty expression
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "dig" stuck at VCC
Info: Implemented 109 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 12 output pins
    Info: Implemented 90 logic cells
    Info: Implemented 1 User Flash Memory blocks
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Wed Jan 02 13:01:12 2008
    Info: Elapsed time: 00:00:02