main.map.qmsg

Altera epm240 的ufm调用。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 02 13:01:11 2008 " "Info: Processing started: Wed Jan 02 13:01:11 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off MAX_UFM -c Main " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MAX_UFM -c Main" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "UFM.v 2 2 " "Info: Found 2 design units, including 2 entities, in source file UFM.v" { { "Info" "ISGN_ENTITY_NAME" "1 UFM_altufm_parallel_nqi " "Info: Found entity 1: UFM_altufm_parallel_nqi" {  } { { "UFM.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/UFM.v" 44 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 UFM " "Info: Found entity 2: UFM" {  } { { "UFM.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/UFM.v" 508 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "main.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file main.v" { { "Info" "ISGN_ENTITY_NAME" "1 MAIN " "Info: Found entity 1: MAIN" {  } { { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "MAIN " "Info: Elaborating entity \"MAIN\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM UFM:ufm " "Info: Elaborating entity \"UFM\" for hierarchy \"UFM:ufm\"" {  } { { "main.v" "ufm" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 53 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "UFM_altufm_parallel_nqi UFM:ufm\|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component " "Info: Elaborating entity \"UFM_altufm_parallel_nqi\" for hierarchy \"UFM:ufm\|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component\"" {  } { { "UFM.v" "UFM_altufm_parallel_nqi_component" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/UFM.v" 533 -1 0 } }  } 0}
{ "Info" "IVRFX_VERI_PORT_DELIBERATELY_NOT_CONNECTED" "busy maxii_ufm_block1 UFM.v(393) " "Info: (10265) Verilog HDL Module Instantiation information at UFM.v(393): instance \"maxii_ufm_block1\" connects port \"busy\" to an empty expression" {  } { { "UFM.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/UFM.v" 393 0 0 } }  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dig VCC " "Warning: Pin \"dig\" stuck at VCC" {  } { { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 19 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "109 " "Info: Implemented 109 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "90 " "Info: Implemented 90 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_UFMS" "1 " "Info: Implemented 1 User Flash Memory blocks" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 02 13:01:12 2008 " "Info: Processing ended: Wed Jan 02 13:01:12 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}