main.tan.qmsg

Altera epm240 的ufm调用。

{ "Info" "ITDB_FULL_TCO_RESULT" "clkOSC clkOut timer\[24\] 11.975 ns register " "Info: tco from clock \"clkOSC\" to destination pin \"clkOut\" through register \"timer\[24\]\" is 11.975 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkOSC source 7.202 ns + Longest register " "Info: + Longest clock path from clock \"clkOSC\" to source register is 7.202 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkOSC 1 CLK PIN_64 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_64; Fanout = 1; CLK Node = 'clkOSC'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "" { clkOSC } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.776 ns) + CELL(0.200 ns) 3.139 ns clk~7 2 COMB LC_X5_Y3_N2 25 " "Info: 2: + IC(1.776 ns) + CELL(0.200 ns) = 3.139 ns; Loc. = LC_X5_Y3_N2; Fanout = 25; COMB Node = 'clk~7'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "1.976 ns" { clkOSC clk~7 } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.145 ns) + CELL(0.918 ns) 7.202 ns timer\[24\] 3 REG LC_X4_Y3_N7 3 " "Info: 3: + IC(3.145 ns) + CELL(0.918 ns) = 7.202 ns; Loc. = LC_X4_Y3_N7; Fanout = 3; REG Node = 'timer\[24\]'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "4.063 ns" { clk~7 timer[24] } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.281 ns 31.67 % " "Info: Total cell delay = 2.281 ns ( 31.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.921 ns 68.33 % " "Info: Total interconnect delay = 4.921 ns ( 68.33 % )" {  } {  } 0}  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[24] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[24] } { 0.000ns 0.000ns 1.776ns 3.145ns } { 0.000ns 1.163ns 0.200ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.397 ns + Longest register pin " "Info: + Longest register to pin delay is 4.397 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns timer\[24\] 1 REG LC_X4_Y3_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y3_N7; Fanout = 3; REG Node = 'timer\[24\]'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "" { timer[24] } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.075 ns) + CELL(2.322 ns) 4.397 ns clkOut 2 PIN PIN_85 0 " "Info: 2: + IC(2.075 ns) + CELL(2.322 ns) = 4.397 ns; Loc. = PIN_85; Fanout = 0; PIN Node = 'clkOut'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "4.397 ns" { timer[24] clkOut } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 23 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns 52.81 % " "Info: Total cell delay = 2.322 ns ( 52.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.075 ns 47.19 % " "Info: Total interconnect delay = 2.075 ns ( 47.19 % )" {  } {  } 0}  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "4.397 ns" { timer[24] clkOut } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "4.397 ns" { timer[24] clkOut } { 0.000ns 2.075ns } { 0.000ns 2.322ns } } }  } 0}  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[24] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[24] } { 0.000ns 0.000ns 1.776ns 3.145ns } { 0.000ns 1.163ns 0.200ns 0.918ns } } } { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "4.397 ns" { timer[24] clkOut } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "4.397 ns" { timer[24] clkOut } { 0.000ns 2.075ns } { 0.000ns 2.322ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "ps_ csRam_ 9.277 ns Longest " "Info: Longest tpd from source pin \"ps_\" to destination pin \"csRam_\" is 9.277 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns ps_ 1 PIN PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_17; Fanout = 1; PIN Node = 'ps_'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "" { ps_ } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.667 ns) + CELL(0.511 ns) 6.310 ns csRam_~0 2 COMB LC_X2_Y4_N0 1 " "Info: 2: + IC(4.667 ns) + CELL(0.511 ns) = 6.310 ns; Loc. = LC_X2_Y4_N0; Fanout = 1; COMB Node = 'csRam_~0'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "5.178 ns" { ps_ csRam_~0 } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.645 ns) + CELL(2.322 ns) 9.277 ns csRam_ 3 PIN PIN_1 0 " "Info: 3: + IC(0.645 ns) + CELL(2.322 ns) = 9.277 ns; Loc. = PIN_1; Fanout = 0; PIN Node = 'csRam_'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "2.967 ns" { csRam_~0 csRam_ } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.965 ns 42.74 % " "Info: Total cell delay = 3.965 ns ( 42.74 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.312 ns 57.26 % " "Info: Total interconnect delay = 5.312 ns ( 57.26 % )" {  } {  } 0}  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "9.277 ns" { ps_ csRam_~0 csRam_ } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "9.277 ns" { ps_ ps_~combout csRam_~0 csRam_ } { 0.000ns 0.000ns 4.667ns 0.645ns } { 0.000ns 1.132ns 0.511ns 2.322ns } } }  } 0}
{ "Info" "ITAN_REQUIREMENTS_MET" "" "Info: All timing requirements were met. See Report window for more details." {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 02 13:01:19 2008 " "Info: Processing ended: Wed Jan 02 13:01:19 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}