main.tan.qmsg

Altera epm240 的ufm调用。

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "UFM:ufm\|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component\|dffe12 " "Info: Detected ripple clock \"UFM:ufm\|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component\|dffe12\" as buffer" {  } { { "UFM.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/UFM.v" 76 -1 0 } } { "f:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "UFM:ufm\|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component\|dffe12" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "UFM:ufm\|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component\|dffe13 " "Info: Detected ripple clock \"UFM:ufm\|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component\|dffe13\" as buffer" {  } { { "UFM.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/UFM.v" 77 -1 0 } } { "f:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "UFM:ufm\|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component\|dffe13" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "clk~7 " "Info: Detected gated clock \"clk~7\" as buffer" {  } { { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 29 -1 0 } } { "f:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk~7" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "UFM:ufm\|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component\|ufm_arclk " "Info: Detected gated clock \"UFM:ufm\|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component\|ufm_arclk\" as buffer" {  } { { "UFM.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/UFM.v" 136 -1 0 } } { "f:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "UFM:ufm\|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component\|ufm_arclk" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "UFM:ufm\|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component\|ufm_drclk " "Info: Detected gated clock \"UFM:ufm\|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component\|ufm_drclk\" as buffer" {  } { { "UFM.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/UFM.v" 140 -1 0 } } { "f:/program files/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "f:/program files/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "UFM:ufm\|UFM_altufm_parallel_nqi:UFM_altufm_parallel_nqi_component\|ufm_drclk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clkOSC register timer\[2\] register timer\[21\] 14.432 ns " "Info: Slack time is 14.432 ns for clock \"clkOSC\" between source register \"timer\[2\]\" and destination register \"timer\[21\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "179.6 MHz 5.568 ns " "Info: Fmax is 179.6 MHz (period= 5.568 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.291 ns + Largest register register " "Info: + Largest register to register requirement is 19.291 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clkOSC 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clkOSC\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clkOSC 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clkOSC\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkOSC destination 7.202 ns + Shortest register " "Info: + Shortest clock path from clock \"clkOSC\" to destination register is 7.202 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkOSC 1 CLK PIN_64 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_64; Fanout = 1; CLK Node = 'clkOSC'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "" { clkOSC } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.776 ns) + CELL(0.200 ns) 3.139 ns clk~7 2 COMB LC_X5_Y3_N2 25 " "Info: 2: + IC(1.776 ns) + CELL(0.200 ns) = 3.139 ns; Loc. = LC_X5_Y3_N2; Fanout = 25; COMB Node = 'clk~7'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "1.976 ns" { clkOSC clk~7 } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.145 ns) + CELL(0.918 ns) 7.202 ns timer\[21\] 3 REG LC_X4_Y3_N4 3 " "Info: 3: + IC(3.145 ns) + CELL(0.918 ns) = 7.202 ns; Loc. = LC_X4_Y3_N4; Fanout = 3; REG Node = 'timer\[21\]'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "4.063 ns" { clk~7 timer[21] } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.281 ns 31.67 % " "Info: Total cell delay = 2.281 ns ( 31.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.921 ns 68.33 % " "Info: Total interconnect delay = 4.921 ns ( 68.33 % )" {  } {  } 0}  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[21] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[21] } { 0.000ns 0.000ns 1.776ns 3.145ns } { 0.000ns 1.163ns 0.200ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkOSC source 7.202 ns - Longest register " "Info: - Longest clock path from clock \"clkOSC\" to source register is 7.202 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkOSC 1 CLK PIN_64 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_64; Fanout = 1; CLK Node = 'clkOSC'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "" { clkOSC } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.776 ns) + CELL(0.200 ns) 3.139 ns clk~7 2 COMB LC_X5_Y3_N2 25 " "Info: 2: + IC(1.776 ns) + CELL(0.200 ns) = 3.139 ns; Loc. = LC_X5_Y3_N2; Fanout = 25; COMB Node = 'clk~7'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "1.976 ns" { clkOSC clk~7 } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.145 ns) + CELL(0.918 ns) 7.202 ns timer\[2\] 3 REG LC_X2_Y3_N5 3 " "Info: 3: + IC(3.145 ns) + CELL(0.918 ns) = 7.202 ns; Loc. = LC_X2_Y3_N5; Fanout = 3; REG Node = 'timer\[2\]'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "4.063 ns" { clk~7 timer[2] } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.281 ns 31.67 % " "Info: Total cell delay = 2.281 ns ( 31.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.921 ns 68.33 % " "Info: Total interconnect delay = 4.921 ns ( 68.33 % )" {  } {  } 0}  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[2] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[2] } { 0.000ns 0.000ns 1.776ns 3.145ns } { 0.000ns 1.163ns 0.200ns 0.918ns } } }  } 0}  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[21] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[21] } { 0.000ns 0.000ns 1.776ns 3.145ns } { 0.000ns 1.163ns 0.200ns 0.918ns } } } { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[2] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[2] } { 0.000ns 0.000ns 1.776ns 3.145ns } { 0.000ns 1.163ns 0.200ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns - " "Info: - Micro setup delay of destination is 0.333 ns" {  } { { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0}  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[21] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[21] } { 0.000ns 0.000ns 1.776ns 3.145ns } { 0.000ns 1.163ns 0.200ns 0.918ns } } } { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[2] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[2] } { 0.000ns 0.000ns 1.776ns 3.145ns } { 0.000ns 1.163ns 0.200ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.859 ns - Longest register register " "Info: - Longest register to register delay is 4.859 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns timer\[2\] 1 REG LC_X2_Y3_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y3_N5; Fanout = 3; REG Node = 'timer\[2\]'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "" { timer[2] } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.892 ns) + CELL(0.978 ns) 1.870 ns timer\[2\]~264 2 COMB LC_X2_Y3_N5 2 " "Info: 2: + IC(0.892 ns) + CELL(0.978 ns) = 1.870 ns; Loc. = LC_X2_Y3_N5; Fanout = 2; COMB Node = 'timer\[2\]~264'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "1.870 ns" { timer[2] timer[2]~264 } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 1.993 ns timer\[3\]~260 3 COMB LC_X2_Y3_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 1.993 ns; Loc. = LC_X2_Y3_N6; Fanout = 2; COMB Node = 'timer\[3\]~260'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "0.123 ns" { timer[2]~264 timer[3]~260 } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.116 ns timer\[4\]~256 4 COMB LC_X2_Y3_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.116 ns; Loc. = LC_X2_Y3_N7; Fanout = 2; COMB Node = 'timer\[4\]~256'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "0.123 ns" { timer[3]~260 timer[4]~256 } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 2.239 ns timer\[5\]~252 5 COMB LC_X2_Y3_N8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.239 ns; Loc. = LC_X2_Y3_N8; Fanout = 2; COMB Node = 'timer\[5\]~252'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "0.123 ns" { timer[4]~256 timer[5]~252 } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.399 ns) 2.638 ns timer\[6\]~248 6 COMB LC_X2_Y3_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.399 ns) = 2.638 ns; Loc. = LC_X2_Y3_N9; Fanout = 6; COMB Node = 'timer\[6\]~248'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "0.399 ns" { timer[5]~252 timer[6]~248 } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.246 ns) 2.884 ns timer\[11\]~228 7 COMB LC_X3_Y3_N4 6 " "Info: 7: + IC(0.000 ns) + CELL(0.246 ns) = 2.884 ns; Loc. = LC_X3_Y3_N4; Fanout = 6; COMB Node = 'timer\[11\]~228'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "0.246 ns" { timer[6]~248 timer[11]~228 } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.349 ns) 3.233 ns timer\[16\]~208 8 COMB LC_X3_Y3_N9 6 " "Info: 8: + IC(0.000 ns) + CELL(0.349 ns) = 3.233 ns; Loc. = LC_X3_Y3_N9; Fanout = 6; COMB Node = 'timer\[16\]~208'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "0.349 ns" { timer[11]~228 timer[16]~208 } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.626 ns) 4.859 ns timer\[21\] 9 REG LC_X4_Y3_N4 3 " "Info: 9: + IC(0.000 ns) + CELL(1.626 ns) = 4.859 ns; Loc. = LC_X4_Y3_N4; Fanout = 3; REG Node = 'timer\[21\]'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "1.626 ns" { timer[16]~208 timer[21] } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.967 ns 81.64 % " "Info: Total cell delay = 3.967 ns ( 81.64 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.892 ns 18.36 % " "Info: Total interconnect delay = 0.892 ns ( 18.36 % )" {  } {  } 0}  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "4.859 ns" { timer[2] timer[2]~264 timer[3]~260 timer[4]~256 timer[5]~252 timer[6]~248 timer[11]~228 timer[16]~208 timer[21] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "4.859 ns" { timer[2] timer[2]~264 timer[3]~260 timer[4]~256 timer[5]~252 timer[6]~248 timer[11]~228 timer[16]~208 timer[21] } { 0.000ns 0.892ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.123ns 0.399ns 0.246ns 0.349ns 1.626ns } } }  } 0}  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[21] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[21] } { 0.000ns 0.000ns 1.776ns 3.145ns } { 0.000ns 1.163ns 0.200ns 0.918ns } } } { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[2] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[2] } { 0.000ns 0.000ns 1.776ns 3.145ns } { 0.000ns 1.163ns 0.200ns 0.918ns } } } { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "4.859 ns" { timer[2] timer[2]~264 timer[3]~260 timer[4]~256 timer[5]~252 timer[6]~248 timer[11]~228 timer[16]~208 timer[21] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "4.859 ns" { timer[2] timer[2]~264 timer[3]~260 timer[4]~256 timer[5]~252 timer[6]~248 timer[11]~228 timer[16]~208 timer[21] } { 0.000ns 0.892ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.978ns 0.123ns 0.123ns 0.123ns 0.399ns 0.246ns 0.349ns 1.626ns } } }  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clkOSC register timer\[6\] register timer\[6\] 2.107 ns " "Info: Minimum slack time is 2.107 ns for clock \"clkOSC\" between source register \"timer\[6\]\" and destination register \"timer\[6\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.952 ns + Shortest register register " "Info: + Shortest register to register delay is 1.952 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns timer\[6\] 1 REG LC_X2_Y3_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y3_N9; Fanout = 2; REG Node = 'timer\[6\]'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "" { timer[6] } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.891 ns) + CELL(1.061 ns) 1.952 ns timer\[6\] 2 REG LC_X2_Y3_N9 2 " "Info: 2: + IC(0.891 ns) + CELL(1.061 ns) = 1.952 ns; Loc. = LC_X2_Y3_N9; Fanout = 2; REG Node = 'timer\[6\]'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "1.952 ns" { timer[6] timer[6] } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.061 ns 54.35 % " "Info: Total cell delay = 1.061 ns ( 54.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.891 ns 45.65 % " "Info: Total interconnect delay = 0.891 ns ( 45.65 % )" {  } {  } 0}  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "1.952 ns" { timer[6] timer[6] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "1.952 ns" { timer[6] timer[6] } { 0.0ns 0.891ns } { 0.0ns 1.061ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.155 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.155 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clkOSC 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clkOSC\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clkOSC 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clkOSC\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkOSC destination 7.202 ns + Longest register " "Info: + Longest clock path from clock \"clkOSC\" to destination register is 7.202 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkOSC 1 CLK PIN_64 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_64; Fanout = 1; CLK Node = 'clkOSC'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "" { clkOSC } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.776 ns) + CELL(0.200 ns) 3.139 ns clk~7 2 COMB LC_X5_Y3_N2 25 " "Info: 2: + IC(1.776 ns) + CELL(0.200 ns) = 3.139 ns; Loc. = LC_X5_Y3_N2; Fanout = 25; COMB Node = 'clk~7'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "1.976 ns" { clkOSC clk~7 } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.145 ns) + CELL(0.918 ns) 7.202 ns timer\[6\] 3 REG LC_X2_Y3_N9 2 " "Info: 3: + IC(3.145 ns) + CELL(0.918 ns) = 7.202 ns; Loc. = LC_X2_Y3_N9; Fanout = 2; REG Node = 'timer\[6\]'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "4.063 ns" { clk~7 timer[6] } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.281 ns 31.67 % " "Info: Total cell delay = 2.281 ns ( 31.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.921 ns 68.33 % " "Info: Total interconnect delay = 4.921 ns ( 68.33 % )" {  } {  } 0}  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[6] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[6] } { 0.0ns 0.0ns 1.776ns 3.145ns } { 0.0ns 1.163ns 0.2ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkOSC source 7.202 ns - Shortest register " "Info: - Shortest clock path from clock \"clkOSC\" to source register is 7.202 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkOSC 1 CLK PIN_64 1 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_64; Fanout = 1; CLK Node = 'clkOSC'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "" { clkOSC } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 13 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.776 ns) + CELL(0.200 ns) 3.139 ns clk~7 2 COMB LC_X5_Y3_N2 25 " "Info: 2: + IC(1.776 ns) + CELL(0.200 ns) = 3.139 ns; Loc. = LC_X5_Y3_N2; Fanout = 25; COMB Node = 'clk~7'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "1.976 ns" { clkOSC clk~7 } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 29 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.145 ns) + CELL(0.918 ns) 7.202 ns timer\[6\] 3 REG LC_X2_Y3_N9 2 " "Info: 3: + IC(3.145 ns) + CELL(0.918 ns) = 7.202 ns; Loc. = LC_X2_Y3_N9; Fanout = 2; REG Node = 'timer\[6\]'" {  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "4.063 ns" { clk~7 timer[6] } "NODE_NAME" } "" } } { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.281 ns 31.67 % " "Info: Total cell delay = 2.281 ns ( 31.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.921 ns 68.33 % " "Info: Total interconnect delay = 4.921 ns ( 68.33 % )" {  } {  } 0}  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[6] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[6] } { 0.0ns 0.0ns 1.776ns 3.145ns } { 0.0ns 1.163ns 0.2ns 0.918ns } } }  } 0}  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[6] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[6] } { 0.0ns 0.0ns 1.776ns 3.145ns } { 0.0ns 1.163ns 0.2ns 0.918ns } } } { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[6] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[6] } { 0.0ns 0.0ns 1.776ns 3.145ns } { 0.0ns 1.163ns 0.2ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "main.v" "" { Text "D:/My Documents/Project/FPGA/MAX_UFM/0000/main.v" 22 -1 0 } }  } 0}  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[6] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[6] } { 0.0ns 0.0ns 1.776ns 3.145ns } { 0.0ns 1.163ns 0.2ns 0.918ns } } } { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[6] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[6] } { 0.0ns 0.0ns 1.776ns 3.145ns } { 0.0ns 1.163ns 0.2ns 0.918ns } } }  } 0}  } { { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "1.952 ns" { timer[6] timer[6] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "1.952 ns" { timer[6] timer[6] } { 0.0ns 0.891ns } { 0.0ns 1.061ns } } } { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[6] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[6] } { 0.0ns 0.0ns 1.776ns 3.145ns } { 0.0ns 1.163ns 0.2ns 0.918ns } } } { "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" "" { Report "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/Main_cmp.qrpt" Compiler "Main" "UNKNOWN" "V1" "D:/My Documents/Project/FPGA/MAX_UFM/0000/db/MAX_UFM.quartus_db" { Floorplan "D:/My Documents/Project/FPGA/MAX_UFM/0000/" "" "7.202 ns" { clkOSC clk~7 timer[6] } "NODE_NAME" } "" } } { "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "f:/program files/altera/quartus50/bin/Technology_Viewer.qrui" "7.202 ns" { clkOSC clkOSC~combout clk~7 timer[6] } { 0.0ns 0.0ns 1.776ns 3.145ns } { 0.0ns 1.163ns 0.2ns 0.918ns } } }  } 0}