rsencoder.v

RS编码的verilog源代码

///  Reed-Solomon Encoder (31,19,6)  ///  

module RSEncoder(clk19_5,clk31_5,reset,start,
                 bitin,bitinstart,bitout,bitoutstart,
                 encodein,invencodeout,
                 wordstart1,wordstart2,ramout,rdaddress,wraddress);

input clk19_5,clk31_5;
input reset,start;
input bitin,bitinstart;

output bitout,bitoutstart,wordstart1,wordstart2;
output[4:0] encodein,invencodeout,ramout,rdaddress,wraddress;

wire clk19,clk31;
wire wordstart1,wordstart2;
wire rdclocken,wrclocken,wren,data19;
wire[4:0] rdaddress,wraddress;
wire[4:0] ramout;
wire[0:4] invramout,encodeout; 


divide5  dividea(clk19_5, 1, clk19);
divide5  divideb(clk31_5, 1, clk31);

assign invramout[4]=ramout[4];
assign invramout[3]=ramout[3];
assign invramout[2]=ramout[2];
assign invramout[1]=ramout[1];
assign invramout[0]=ramout[0];

assign invencodeout[4]=encodeout[4];
assign invencodeout[3]=encodeout[3];
assign invencodeout[2]=encodeout[2];
assign invencodeout[1]=encodeout[1];
assign invencodeout[0]=encodeout[0];          

Bit2Dec       A(reset,bitinstart,clk19_5,bitin,
                clk19,encodein,wordstart1);

fifo_encode   B(clk19,clk31,reset,wordstart1,rdaddress,rdclocken,
                wraddress,wrclocken,wren,data19,wordstart2);

lpm_ram_dp0   C(encodein,rdaddress,clk31,rdclocken,
                wraddress,clk19,wrclocken,wren,ramout);

rsenc         D(clk31,reset,start,data19,invramout,encodeout); 

Dec2Bit       E(reset,wordstart2,clk31,invencodeout,
                clk31_5,bitout,bitoutstart);

endmodule