source_nrz.v

来自「RS编码的verilog源代码」· Verilog 代码 · 共 35 行

module nrz(clk,reset,start,out,datastart);

  input clk, reset, start;
  output out,datastart;
  reg  out,datastart;
  reg c1,c2,c3,c4,c5;
  reg[2:0] cnt;

  always @ (posedge clk or negedge reset)
    begin
          if(~reset) 
          begin 
              out<=0;
              cnt=0;
              datastart=0;
          end
          else if (start)
          begin
                 if(cnt==7) cnt=5;  
                 else    cnt=cnt+1; 
                 if(cnt==4) datastart=1;
                 if(cnt==5) datastart=0;               

                 c2<=c1;
	             c3<=c2;
	             c4<=c3;
	             c5<=c4;
	             c1<=(c3^c5)^(~(c1|c2|c3|c4|c5));
                 out<=c5;
          end
          else  out<=0;
    end
endmodule