ram_fifo_all.v

RS编码的verilog源代码

//各个RAM的输入输出控制
module fifo_encode(clk1,clk2,reset,start,rdaddress,rdclocken,
                    wraddress,wrclocken,wren,data19,wordstart); 

input start, reset;
input clk1, clk2;
output[4:0] rdaddress;
reg[4:0] rdaddress;
output rdclocken;
output[4:0] wraddress;
reg[4:0] wraddress;
output wrclocken, wren;
output data19, wordstart;
reg rdclocken, wrclocken,wren,data19,wordstart;
reg [4:0] temp;
reg [5:0] temp1;
reg enable;

always @ (posedge start or negedge reset)
begin
  if(~reset) enable=0;
  else   enable=1;
end


always @ (posedge clk1 or negedge reset)
begin
     if (~reset)
     begin
          wraddress=0;
          wrclocken=0;
          wren=0;
          temp=1;
     end
     else if (enable)
     begin
          wren=1;   
          wrclocken=1;      
          if (wraddress>=19)
                   wraddress=1;
          else     wraddress=wraddress+1; 
          if(temp>=16) temp=16;
          else  temp=temp+1;
     end
end

//assign clk3=clk2&(temp==16);

always @ (posedge clk2 or negedge reset)
begin
     if (~reset)
     begin
          rdaddress=0;
          rdclocken=0;
          data19=0;
          wordstart=0;
          temp1=0;
     end
     else if (enable&(temp==16))
     begin
          rdclocken=(temp==16);//在写入16个数后再读 
          if (temp1>=31)  
              begin
                 wordstart=0;  
                 temp1=1;
                 rdaddress=1; 
              end 
          else 
              begin
                 temp1=temp1+1; 
                 rdaddress=temp1; 
                 wordstart=(temp1==2);  
              end 
    
          if((rdaddress>=3)&&(rdaddress<=21))  data19=1;
          else   data19=0;
     end

end

endmodule  




//-----------------------------------------------------------//



module fifo_decode(clk1,clk2,reset,dataoutstart,rdaddress,rdclocken,
                    wraddress,wrclocken,wren,wordstart); 

input dataoutstart,reset;
input clk1, clk2;
output[4:0] rdaddress,wraddress;
reg[4:0] rdaddress,wraddress;
output rdclocken, wrclocken, wren, wordstart;
reg rdclocken, wrclocken,wren,wordstart,isword1,isword2;
reg [4:0] temp2;
reg [5:0] temp1;


always @ (posedge clk1 or negedge reset or posedge dataoutstart)
begin
     if (~reset)
     begin
          wraddress=0;
          wrclocken=0;
          wren=0;
          temp1=0;
          isword1=0;  
          isword2=0; 
     end
     else if(dataoutstart)
     begin
          wraddress=1;
          wren=1;
          temp1=1;
          isword1=1;
     end
     else if (isword1)
     begin
          if (temp1>=57)  
              begin
                 temp1=1;
                 wraddress=1; 
                 wren=1;   
                 wrclocken=1;      
              end 
          else if(temp1>=31) 
              begin
                 wraddress=0; 
                 temp1=temp1+1; 
              end    
          else 
              begin
                 if(temp1==5)
                 begin
                 isword2=1;  
                 end            
                 temp1=temp1+1; 
                 wraddress=temp1; 
                 wren=1;   
                 wrclocken=1;  
              end     
     end
end



always @ (posedge clk2 or negedge reset)
begin
     if (~reset)
     begin
          rdaddress=0;
          rdclocken=0;
          wordstart=0;
          temp2=0;
     end
     else if (isword2)
     begin
          rdclocken=1;
          if (temp2>=19)  
              begin
                 temp2=1;
                 rdaddress=1; 
              end 
          else 
              begin
                 if(rdaddress==1)
                 begin
                 wordstart=1;  
                 end 
                 else 
                 begin
                 wordstart=0;  
                 end  
                 temp2=temp2+1; 
                 rdaddress=temp2; 
              end      
     end

end

endmodule         



//-----------------------------------------------------------//



module before_decode(clk1,clk2,reset,start,rdaddress,rdclocken,
                    wraddress,wrclocken,wren,inwordstart,wordstart); 

input start, reset;
input clk1, clk2,inwordstart;
output[4:0] rdaddress;
reg[4:0] rdaddress;
output rdclocken;
output[4:0] wraddress;
reg[4:0] wraddress;
output wrclocken, wren;
output  wordstart;
reg rdclocken, wrclocken,wren,wordstart;
reg [4:0] temp;
reg [5:0] temp1;
reg enable;


always @ (posedge inwordstart or negedge reset)
begin
 if (~reset)  enable=0;
 else enable=1;
end


always @ (posedge clk1 or negedge reset)
begin
     if (~reset)
     begin
          wraddress=0;
          wrclocken=0;
          wren=0;
          temp=1;
     end
     else if (enable)
     begin
          wren=1;   
          wrclocken=1;      
          if (wraddress>=31)
                   wraddress=1;
          else     wraddress=wraddress+1; 
          if(temp>=24) temp=24;
          else  temp=temp+1;
     end
end

//assign clk3=clk2&(temp==24);

always @ (posedge clk2 or negedge reset)
begin
     if (~reset)
     begin
          rdaddress=0;
          rdclocken=0;
          wordstart=0;
          temp1=0;
     end
     else if (enable&(temp==24))
     begin
          rdclocken=(temp==24);//在写入24个数后再读 
          if (temp1>=57)  
              begin
                 wordstart=0;  
                 temp1=1;
                 rdaddress=1; 
              end 
          else if(temp1>=31) 
              begin
                 rdaddress=0; 
                 temp1=temp1+1; 
                 wordstart=0;  
              end    
          else 
              begin
                 temp1=temp1+1; 
                 rdaddress=temp1; 
                 wordstart=(temp1==2);  
              end 
     end

end

endmodule