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RS编码的verilog源代码

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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+---------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+
; Type                                                                ; Slack     ; Required Time                    ; Actual Time                      ; From                                                             ; To                                                                                                                             ; From Clock                                           ; To Clock                                             ; Failed Paths ;
+---------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+
; Worst-case tsu                                                      ; N/A       ; None                             ; 10.786 ns                        ; reset                                                            ; RSDecoder:inst1|Bit2Dec:Bit2Dec|c5                                                                                             ; --                                                   ; clk                                                  ; 0            ;
; Worst-case tco                                                      ; N/A       ; None                             ; 14.003 ns                        ; RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1.st1_11 ; fail                                                                                                                           ; clk                                                  ; --                                                   ; 0            ;
; Worst-case th                                                       ; N/A       ; None                             ; -1.442 ns                        ; reset                                                            ; nrz:inst2|c1                                                                                                                   ; --                                                   ; clk                                                  ; 0            ;
; Clock Setup: 'Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0' ; -9.142 ns ; 36.73 MHz ( period = 27.224 ns ) ; N/A                              ; RSEncoder:inst|fifo_encode:B|temp[0]                             ; RSEncoder:inst|fifo_encode:B|rdclocken                                                                                         ; clk                                                  ; Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 ; 48           ;
; Clock Setup: 'clk'                                                  ; -2.790 ns ; 67.59 MHz ( period = 14.796 ns ) ; 49.08 MHz ( period = 20.376 ns ) ; RSDecoder:inst1|Dec2Bit:Dec2Bit|enable                           ; RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0]                                                                                        ; clk                                                  ; clk                                                  ; 163          ;
; Clock Hold: 'clk'                                                   ; -3.579 ns ; 67.59 MHz ( period = 14.796 ns ) ; N/A                              ; RSEncoder:inst|Bit2Dec:A|out[0]                                  ; RSEncoder:inst|lpm_ram_dp0:C|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|ram_block1a3~porta_datain_reg4     ; clk                                                  ; clk                                                  ; 23           ;
; Clock Hold: 'Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0'  ; -3.147 ns ; 36.73 MHz ( period = 27.224 ns ) ; N/A                              ; RSDecoder:inst1|Bit2Dec:Bit2Dec|out[4]                           ; RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated|ram_block1a3~porta_datain_reg4 ; Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 ; Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 ; 16           ;
; Total number of failed paths                                        ;           ;                                  ;                                  ;                                                                  ;                                                                                                                                ;                                                      ;                                                      ; 250          ;
+---------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+------------------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;