top.v

RS编码的verilog源代码

//RS(31,19,6) Encoder and Decoder     

module top(clk,reset,start,error,
           bitin,bitinstart,encodeoutbit,bitout,bitoutstart,
           encodein,encodeout,decodein,decodeout,
           errfound, decode_fail,adderror,
           decodeinstart1,ram1outstart,dataoutstart,decodeoutstart,ram1out,decodedataout,
           wraddress1,rdaddress1,wraddress2,rdaddress2);

input clk, start, reset;
input error;
output bitin,bitinstart,encodeoutbit,bitout,bitoutstart;
output [4:0] encodein,encodeout,decodein,decodeout;
output adderror;

output decodeinstart1,ram1outstart,dataoutstart,decodeoutstart;
output[4:0] ram1out,decodedataout,wraddress1,rdaddress1,wraddress2,rdaddress2;

output errfound, decode_fail; 
wire clk19,clk19_5,clk31,clk31_5,clk57;
wire encodeoutbit,decodeinstart,encodebitoutstart;

//divide5  dividea(clk, 1, clk57);
//divide3  dividec(clk, 1, clk19);
//pll      p31_57(0,clk,clk31);
Clock    clock(clk,clk19,clk31);
nrz  nrz(clk19,reset,start,bitin,bitinstart);//信号源产生信号


RSEncoder  RSEncoder(clk19,clk31,reset,start,
                 bitin,bitinstart,encodeoutbit,encodebitoutstart,
                 encodein,encodeout,
                 wordstart1,wordstart2,ramout,rdaddress,wraddress);

//assign adderror=error^encodeoutbit;
mydff data(error^encodeoutbit,adderror,clk31,reset);
mydff datastart(encodebitoutstart,decodeinstart,clk31,reset);

RSDecoder  RSDecoder(clk19,clk31,clk,reset,start,
                 adderror,decodeinstart,errfound,decode_fail,bitout,bitoutstart,
                 decodein,ram1out,decodedataout,decodeout,
                  decodeinstart1,ram1outstart,dataoutstart,decodeoutstart,
                  wraddress1,rdaddress1,wraddress2,rdaddress2);
 
endmodule


module mydff(D,Q,clk,reset);
input D,clk,reset;
output Q;
reg Q;
always@(posedge clk)
   if(reset!=0) Q=D;
      else   Q=0;
endmodule