error.v

RS编码的verilog源代码

module error(clk,errorout);
input clk;
output errorout;
reg errorout;
reg[7:0] cnt;

always@(posedge clk)
begin
     cnt<=cnt+1;
     if(cnt==11|cnt==89|cnt==140|cnt==170|cnt==200|cnt==256)
            errorout<=1;
     else   errorout<=0;
end
endmodule