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📁 RS编码的verilog源代码
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PARAMETER_UNKNOWN
DEF
C2_PH
0
PARAMETER_UNKNOWN
DEF
C3_PH
0
PARAMETER_UNKNOWN
DEF
C4_PH
0
PARAMETER_UNKNOWN
DEF
C5_PH
0
PARAMETER_UNKNOWN
DEF
L0_HIGH
1
PARAMETER_UNKNOWN
DEF
L1_HIGH
1
PARAMETER_UNKNOWN
DEF
G0_HIGH
1
PARAMETER_UNKNOWN
DEF
G1_HIGH
1
PARAMETER_UNKNOWN
DEF
G2_HIGH
1
PARAMETER_UNKNOWN
DEF
G3_HIGH
1
PARAMETER_UNKNOWN
DEF
E0_HIGH
1
PARAMETER_UNKNOWN
DEF
E1_HIGH
1
PARAMETER_UNKNOWN
DEF
E2_HIGH
1
PARAMETER_UNKNOWN
DEF
E3_HIGH
1
PARAMETER_UNKNOWN
DEF
L0_LOW
1
PARAMETER_UNKNOWN
DEF
L1_LOW
1
PARAMETER_UNKNOWN
DEF
G0_LOW
1
PARAMETER_UNKNOWN
DEF
G1_LOW
1
PARAMETER_UNKNOWN
DEF
G2_LOW
1
PARAMETER_UNKNOWN
DEF
G3_LOW
1
PARAMETER_UNKNOWN
DEF
E0_LOW
1
PARAMETER_UNKNOWN
DEF
E1_LOW
1
PARAMETER_UNKNOWN
DEF
E2_LOW
1
PARAMETER_UNKNOWN
DEF
E3_LOW
1
PARAMETER_UNKNOWN
DEF
L0_INITIAL
1
PARAMETER_UNKNOWN
DEF
L1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G0_INITIAL
1
PARAMETER_UNKNOWN
DEF
G1_INITIAL
1
PARAMETER_UNKNOWN
DEF
G2_INITIAL
1
PARAMETER_UNKNOWN
DEF
G3_INITIAL
1
PARAMETER_UNKNOWN
DEF
E0_INITIAL
1
PARAMETER_UNKNOWN
DEF
E1_INITIAL
1
PARAMETER_UNKNOWN
DEF
E2_INITIAL
1
PARAMETER_UNKNOWN
DEF
E3_INITIAL
1
PARAMETER_UNKNOWN
DEF
L0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
G3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E0_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E1_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E2_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
E3_MODE
BYPASS
PARAMETER_UNKNOWN
DEF
L0_PH
0
PARAMETER_UNKNOWN
DEF
L1_PH
0
PARAMETER_UNKNOWN
DEF
G0_PH
0
PARAMETER_UNKNOWN
DEF
G1_PH
0
PARAMETER_UNKNOWN
DEF
G2_PH
0
PARAMETER_UNKNOWN
DEF
G3_PH
0
PARAMETER_UNKNOWN
DEF
E0_PH
0
PARAMETER_UNKNOWN
DEF
E1_PH
0
PARAMETER_UNKNOWN
DEF
E2_PH
0
PARAMETER_UNKNOWN
DEF
E3_PH
0
PARAMETER_UNKNOWN
DEF
M_PH
0
PARAMETER_UNKNOWN
DEF
C1_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C2_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C3_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C4_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
C5_USE_CASC_IN
0
PARAMETER_UNKNOWN
DEF
CLK0_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK1_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK2_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK3_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK4_COUNTER
G0
PARAMETER_UNKNOWN
DEF
CLK5_COUNTER
G0
PARAMETER_UNKNOWN
DEF
L0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
L1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
G3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E0_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E1_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E2_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
E3_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
M_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
N_TIME_DELAY
0
PARAMETER_UNKNOWN
DEF
EXTCLK3_COUNTER
E3
PARAMETER_UNKNOWN
DEF
EXTCLK2_COUNTER
E2
PARAMETER_UNKNOWN
DEF
EXTCLK1_COUNTER
E1
PARAMETER_UNKNOWN
DEF
EXTCLK0_COUNTER
E0
PARAMETER_UNKNOWN
DEF
ENABLE0_COUNTER
L0
PARAMETER_UNKNOWN
DEF
ENABLE1_COUNTER
L0
PARAMETER_UNKNOWN
DEF
CHARGE_PUMP_CURRENT
2
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_R
 1.000000
PARAMETER_UNKNOWN
DEF
LOOP_FILTER_C
5
PARAMETER_UNKNOWN
DEF
VCO_POST_SCALE
0
PARAMETER_UNKNOWN
DEF
CLK2_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK1_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
CLK0_OUTPUT_FREQUENCY
0
PARAMETER_UNKNOWN
DEF
INTENDED_DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
PORT_CLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA4
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKENA5
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKBAD0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKBAD1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK4
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK5
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDATAOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDONE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKLOSS
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_INCLK1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_INCLK0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_FBIN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PLLENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLKSWITCH
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ARESET
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PFDENA
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANCLK
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANACLR
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANREAD
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANWRITE
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
locked
-1
3
inclk
-1
3
clk
-1
3
areset
-1
3
}
# include_file {
..|..|altera|quartus51|libraries|megafunctions|aglobal51.inc
c49d61e8168d42962ec885e3e17640c2
..|..|altera|quartus51|libraries|megafunctions|stratix_pll.inc
5f8211898149ceae8264a0ea5036254f
..|..|altera|quartus51|libraries|megafunctions|stratixii_pll.inc
6d1985e16ab5f59a1fd6b0ae20978a4e
..|..|altera|quartus51|libraries|megafunctions|cycloneii_pll.inc
39a0d9d1237d1db39c848c3f9faffc
}
# hierarchies {
Clock:inst3|pll:p31_57|altpll:altpll_component
}
# end
# entity
divide3
# storage
db|top.(54).cnf
db|top.(54).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
frequency divider.v
b25576af260f775fa4ced97d84f6e
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
Clock:inst3|divide3:divideb
}
# end
# entity
RSEncoder
# storage
db|top.(55).cnf
db|top.(55).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RSEncoder.v
4e03e7fb767c03e3d16d52d6d08a46
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RSEncoder:inst
}
# end
# entity
fifo_encode
# storage
db|top.(56).cnf
db|top.(56).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RAM_fifo_all.v
68bf367123e6f0544fcb998c86644a7c
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RSEncoder:inst|fifo_encode:B
}
# end
# entity
rsenc
# storage
db|top.(57).cnf
db|top.(57).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rsencode.v
a9c437ffca3dd3178ec688fe6b7eaa
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RSEncoder:inst|rsenc:D
}
# end
# entity
mul
# storage
db|top.(58).cnf
db|top.(58).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rsencode.v
a9c437ffca3dd3178ec688fe6b7eaa
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RSEncoder:inst|rsenc:D|mul:m0
RSEncoder:inst|rsenc:D|mul:m1
RSEncoder:inst|rsenc:D|mul:m2
RSEncoder:inst|rsenc:D|mul:m3
RSEncoder:inst|rsenc:D|mul:m4
RSEncoder:inst|rsenc:D|mul:m5
RSEncoder:inst|rsenc:D|mul:m6
RSEncoder:inst|rsenc:D|mul:m7
RSEncoder:inst|rsenc:D|mul:m8
RSEncoder:inst|rsenc:D|mul:m9
RSEncoder:inst|rsenc:D|mul:m10
RSEncoder:inst|rsenc:D|mul:m11
}
# end
# entity
nrz
# storage
db|top.(59).cnf
db|top.(59).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
source_nrz.v
44c04799e6ba432ca4ae3d5fee2ae
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
nrz:inst2
}
# end
# entity
rs
# storage
db|top.(1).cnf
db|top.(1).cnf
# case_insensitive
# source_file
rs.bdf
4db5ec87cc4989b1a2696719b5ef8
23
# hierarchies {
|
}
# end
# entity
error
# storage
db|top.(0).cnf
db|top.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
error.v
8aa886c80a6e465391745887674c6a2
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
error:inst6
}
# end
# complete
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