top.hif

RS编码的verilog源代码

Version 5.1 Build 216 03/06/2006 Service Pack 2 SJ Full Version
33
1707
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
# entity
RSDecoder
# storage
db|top.(2).cnf
db|top.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RSDecoder.v
ad79402fb998d93b335aada3de8e22bb
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RSDecoder:inst1
}
# end
# entity
divide5
# storage
db|top.(3).cnf
db|top.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
frequency divider.v
b25576af260f775fa4ced97d84f6e
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RSDecoder:inst1|divide5:dividea
RSDecoder:inst1|divide5:divideb
RSDecoder:inst1|divide5:dividec
RSEncoder:inst|divide5:dividea
RSEncoder:inst|divide5:divideb
}
# end
# entity
Bit2Dec
# storage
db|top.(4).cnf
db|top.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
serial_paralled_conversion.v
1e9090bb962671b91e698724a9cca3
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RSDecoder:inst1|Bit2Dec:Bit2Dec
RSEncoder:inst|Bit2Dec:A
}
# end
# entity
before_decode
# storage
db|top.(5).cnf
db|top.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RAM_fifo_all.v
68bf367123e6f0544fcb998c86644a7c
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RSDecoder:inst1|before_decode:before_decode
}
# end
# entity
lpm_ram_dp0
# storage
db|top.(6).cnf
db|top.(6).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
RAM.v
64f12298af93654cd1a0de8fe5125686
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RSDecoder:inst1|lpm_ram_dp0:ram1
RSDecoder:inst1|lpm_ram_dp0:ram2
RSEncoder:inst|lpm_ram_dp0:C
}
# end
# entity
altsyncram
# storage
db|top.(7).cnf
db|top.(7).cnf
# case_insensitive
# source_file
..|..|altera|quartus51|libraries|megafunctions|altsyncram.tdf
6d23188b861aaf86e7848b32051ebea
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
5
PARAMETER_DEC
USR
WIDTHAD_A
5
PARAMETER_DEC
USR
NUMWORDS_A
32
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
5
PARAMETER_DEC
USR
WIDTHAD_B
5
PARAMETER_DEC
USR
NUMWORDS_B
32
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_lva1
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b
-1
3
data_a
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b
-1
3
address_a
-1
3
wren_b
-1
1
addressstall_b
-1
1
addressstall_a
-1
1
aclr1
-1
1
aclr0
-1
1
rden_b
-1
2
data_b
-1
2
byteena_b
-1
2
byteena_a
-1
2
}
# include_file {
..|..|altera|quartus51|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
..|..|altera|quartus51|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
..|..|altera|quartus51|libraries|megafunctions|altsyncram.inc
2d485e3cf75d4048974bdbf0d920cb89
..|..|altera|quartus51|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|altera|quartus51|libraries|megafunctions|aglobal51.inc
c49d61e8168d42962ec885e3e17640c2
..|..|altera|quartus51|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
..|..|altera|quartus51|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
..|..|altera|quartus51|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
..|..|altera|quartus51|libraries|megafunctions|altdpram.inc
4e1931f9814db9f22f22b9eb377c65d6
..|..|altera|quartus51|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
}
# hierarchies {
RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component
RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component
RSEncoder:inst|lpm_ram_dp0:C|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_lva1
# storage
db|top.(8).cnf
db|top.(8).cnf
# case_insensitive
# source_file
db|altsyncram_lva1.tdf
8449d35cbb578debd1a7c7aebd89c95
6
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
-1
3
q_b4
-1
3
q_b3
-1
3
q_b2
-1
3
q_b1
-1
3
q_b0
-1
3
data_a4
-1
3
data_a3
-1
3
data_a2
-1
3
data_a1
-1
3
data_a0
-1
3
clocken1
-1
3
clocken0
-1
3
clock1
-1
3
clock0
-1
3
address_b4
-1
3
address_b3
-1
3
address_b2
-1
3
address_b1
-1
3
address_b0
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
none
0
}
# hierarchies {
RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated
RSDecoder:inst1|lpm_ram_dp0:ram2|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated
RSEncoder:inst|lpm_ram_dp0:C|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated
}
# end
# entity
rsdec
# storage
db|top.(9).cnf
db|top.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rsdecode.v
24de24177675186baeaa3f6c384eca99
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RSDecoder:inst1|rsdec:rsdec
}
# end
# entity
SCblock
# storage
db|top.(10).cnf
db|top.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SCBLOCK.V
ba892a2cf1d0d97c5caa206236251874
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# user_parameter {
st0
00
PARAMETER_BIN
DEF
st1
01
PARAMETER_BIN
DEF
st2
10
PARAMETER_BIN
DEF
}
# hierarchies {
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock
}
# end
# entity
syndcell_0
# storage
db|top.(11).cnf
db|top.(11).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SCBLOCK.V
ba892a2cf1d0d97c5caa206236251874
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0
}
# end
# entity
register5_wlh
# storage
db|top.(12).cnf
db|top.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
common_modules.v
b0f73556532d9521a486fe14a7492
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|register5_wlh:register5bit
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|register5_wlh:register5bit
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|register5_wlh:register5bit
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|register5_wlh:register5bit
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg0
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg1
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg2
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg3
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg4
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg5
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg6
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg7
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg8
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg9
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg10
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg11
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg12
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg13
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg14
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg15
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg16
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg17
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg18
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg19
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg20
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg21
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg22
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg23
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg24
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg25
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg26
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg27
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg28
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg29
RSDecoder:inst1|rsdec:rsdec|fifo_register:fiforeg|register5_wlh:Reg30
}
# end
# entity
gfadder
# storage
db|top.(13).cnf
db|top.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
common_modules.v
b0f73556532d9521a486fe14a7492
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|gfadder:adder
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|gfadder:adder
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|gfadder:adder
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|gfadder:adder
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|gfadder:adder
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|gfadder:adder
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|gfadder:adder
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|gfadder:adder
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|gfadder:adder
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|gfadder:adder
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|gfadder:adder
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|gfadder:adder
RSDecoder:inst1|rsdec:rsdec|gfadder:adder
}
# end
# entity
syndcell_1
# storage
db|top.(14).cnf
db|top.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SCBLOCK.V
ba892a2cf1d0d97c5caa206236251874
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1
}
# end
# entity
syndcell_2
# storage
db|top.(15).cnf
db|top.(15).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SCBLOCK.V
ba892a2cf1d0d97c5caa206236251874
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2
}
# end
# entity
syndcell_3
# storage
db|top.(16).cnf
db|top.(16).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
SCBLOCK.V
ba892a2cf1d0d97c5caa206236251874
7
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3
}
# end
# entity
syndcell_4
# storage
db|top.(17).cnf
db|top.(17).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file