top.tan.qmsg

RS编码的verilog源代码

{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register RSDecoder:inst1\|Dec2Bit:Dec2Bit\|enable register RSDecoder:inst1\|Dec2Bit:Dec2Bit\|buff\[0\] -2.79 ns " "Info: Slack time is -2.79 ns for clock \"clk\" between source register \"RSDecoder:inst1\|Dec2Bit:Dec2Bit\|enable\" and destination register \"RSDecoder:inst1\|Dec2Bit:Dec2Bit\|buff\[0\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "49.08 MHz 20.376 ns " "Info: Fmax is 49.08 MHz (period= 20.376 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.818 ns + Largest register register " "Info: + Largest register to register requirement is -0.818 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "7.398 ns + " "Info: + Setup relationship between source and destination is 7.398 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 14.796 ns " "Info: + Latch edge is 14.796 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 14.796 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 14.796 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 7.398 ns " "Info: - Launch edge is 7.398 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 14.796 ns 7.398 ns inverted 50 " "Info: Clock period of Source clock \"clk\" is 14.796 ns with inverted offset of 7.398 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-7.955 ns + Largest " "Info: + Largest clock skew is -7.955 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.713 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.713 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 11 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 11; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { clk } "NODE_NAME" } "" } } { "rs.bdf" "" { Schematic "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rs.bdf" { { 112 -144 24 128 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns Clock:inst3\|divide3:divideb\|clk_temp2 2 REG LC_X8_Y10_N9 1 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N9; Fanout = 1; REG Node = 'Clock:inst3\|divide3:divideb\|clk_temp2'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "1.680 ns" { clk Clock:inst3|divide3:divideb|clk_temp2 } "NODE_NAME" } "" } } { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.378 ns) 3.527 ns Clock:inst3\|divide3:divideb\|clk_out 3 COMB LC_X8_Y10_N9 39 " "Info: 3: + IC(0.000 ns) + CELL(0.378 ns) = 3.527 ns; Loc. = LC_X8_Y10_N9; Fanout = 39; COMB Node = 'Clock:inst3\|divide3:divideb\|clk_out'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "0.378 ns" { Clock:inst3|divide3:divideb|clk_temp2 Clock:inst3|divide3:divideb|clk_out } "NODE_NAME" } "" } } { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.475 ns) + CELL(0.711 ns) 7.713 ns RSDecoder:inst1\|Dec2Bit:Dec2Bit\|buff\[0\] 4 REG LC_X19_Y11_N3 2 " "Info: 4: + IC(3.475 ns) + CELL(0.711 ns) = 7.713 ns; Loc. = LC_X19_Y11_N3; Fanout = 2; REG Node = 'RSDecoder:inst1\|Dec2Bit:Dec2Bit\|buff\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "4.186 ns" { Clock:inst3|divide3:divideb|clk_out RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0] } "NODE_NAME" } "" } } { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.493 ns ( 45.29 % ) " "Info: Total cell delay = 3.493 ns ( 45.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.220 ns ( 54.71 % ) " "Info: Total interconnect delay = 4.220 ns ( 54.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "7.713 ns" { clk Clock:inst3|divide3:divideb|clk_temp2 Clock:inst3|divide3:divideb|clk_out RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.713 ns" { clk clk~out0 Clock:inst3|divide3:divideb|clk_temp2 Clock:inst3|divide3:divideb|clk_out RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0] } { 0.000ns 0.000ns 0.745ns 0.000ns 3.475ns } { 0.000ns 1.469ns 0.935ns 0.378ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 15.668 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 15.668 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 11 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 11; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { clk } "NODE_NAME" } "" } } { "rs.bdf" "" { Schematic "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rs.bdf" { { 112 -144 24 128 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns Clock:inst3\|divide3:divideb\|clk_temp1 2 REG LC_X8_Y10_N3 3 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N3; Fanout = 3; REG Node = 'Clock:inst3\|divide3:divideb\|clk_temp1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "1.680 ns" { clk Clock:inst3|divide3:divideb|clk_temp1 } "NODE_NAME" } "" } } { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.114 ns) 3.797 ns Clock:inst3\|divide3:divideb\|clk_out 3 COMB LC_X8_Y10_N9 39 " "Info: 3: + IC(0.534 ns) + CELL(0.114 ns) = 3.797 ns; Loc. = LC_X8_Y10_N9; Fanout = 39; COMB Node = 'Clock:inst3\|divide3:divideb\|clk_out'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "0.648 ns" { Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out } "NODE_NAME" } "" } } { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.457 ns) + CELL(0.935 ns) 8.189 ns RSEncoder:inst\|divide5:dividea\|clk_temp1 4 REG LC_X10_Y10_N0 3 " "Info: 4: + IC(3.457 ns) + CELL(0.935 ns) = 8.189 ns; Loc. = LC_X10_Y10_N0; Fanout = 3; REG Node = 'RSEncoder:inst\|divide5:dividea\|clk_temp1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "4.392 ns" { Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 } "NODE_NAME" } "" } } { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.114 ns) 8.845 ns RSDecoder:inst1\|divide5:dividea\|clk_out 5 COMB LC_X10_Y10_N2 44 " "Info: 5: + IC(0.542 ns) + CELL(0.114 ns) = 8.845 ns; Loc. = LC_X10_Y10_N2; Fanout = 44; COMB Node = 'RSDecoder:inst1\|divide5:dividea\|clk_out'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "0.656 ns" { RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out } "NODE_NAME" } "" } } { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.826 ns) + CELL(0.935 ns) 13.606 ns RSDecoder:inst1\|fifo_decode:fifo_decode\|wordstart 6 REG LC_X16_Y11_N8 2 " "Info: 6: + IC(3.826 ns) + CELL(0.935 ns) = 13.606 ns; Loc. = LC_X16_Y11_N8; Fanout = 2; REG Node = 'RSDecoder:inst1\|fifo_decode:fifo_decode\|wordstart'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "4.761 ns" { RSDecoder:inst1|divide5:dividea|clk_out RSDecoder:inst1|fifo_decode:fifo_decode|wordstart } "NODE_NAME" } "" } } { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 97 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.351 ns) + CELL(0.711 ns) 15.668 ns RSDecoder:inst1\|Dec2Bit:Dec2Bit\|enable 7 REG LC_X19_Y11_N5 6 " "Info: 7: + IC(1.351 ns) + CELL(0.711 ns) = 15.668 ns; Loc. = LC_X19_Y11_N5; Fanout = 6; REG Node = 'RSDecoder:inst1\|Dec2Bit:Dec2Bit\|enable'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "2.062 ns" { RSDecoder:inst1|fifo_decode:fifo_decode|wordstart RSDecoder:inst1|Dec2Bit:Dec2Bit|enable } "NODE_NAME" } "" } } { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.213 ns ( 33.27 % ) " "Info: Total cell delay = 5.213 ns ( 33.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.455 ns ( 66.73 % ) " "Info: Total interconnect delay = 10.455 ns ( 66.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "15.668 ns" { clk Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out RSDecoder:inst1|fifo_decode:fifo_decode|wordstart RSDecoder:inst1|Dec2Bit:Dec2Bit|enable } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "15.668 ns" { clk clk~out0 Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out RSDecoder:inst1|fifo_decode:fifo_decode|wordstart RSDecoder:inst1|Dec2Bit:Dec2Bit|enable } { 0.000ns 0.000ns 0.745ns 0.534ns 3.457ns 0.542ns 3.826ns 1.351ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "7.713 ns" { clk Clock:inst3|divide3:divideb|clk_temp2 Clock:inst3|divide3:divideb|clk_out RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.713 ns" { clk clk~out0 Clock:inst3|divide3:divideb|clk_temp2 Clock:inst3|divide3:divideb|clk_out RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0] } { 0.000ns 0.000ns 0.745ns 0.000ns 3.475ns } { 0.000ns 1.469ns 0.935ns 0.378ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "15.668 ns" { clk Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out RSDecoder:inst1|fifo_decode:fifo_decode|wordstart RSDecoder:inst1|Dec2Bit:Dec2Bit|enable } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "15.668 ns" { clk clk~out0 Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out RSDecoder:inst1|fifo_decode:fifo_decode|wordstart RSDecoder:inst1|Dec2Bit:Dec2Bit|enable } { 0.000ns 0.000ns 0.745ns 0.534ns 3.457ns 0.542ns 3.826ns 1.351ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "7.713 ns" { clk Clock:inst3|divide3:divideb|clk_temp2 Clock:inst3|divide3:divideb|clk_out RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.713 ns" { clk clk~out0 Clock:inst3|divide3:divideb|clk_temp2 Clock:inst3|divide3:divideb|clk_out RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0] } { 0.000ns 0.000ns 0.745ns 0.000ns 3.475ns } { 0.000ns 1.469ns 0.935ns 0.378ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "15.668 ns" { clk Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out RSDecoder:inst1|fifo_decode:fifo_decode|wordstart RSDecoder:inst1|Dec2Bit:Dec2Bit|enable } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "15.668 ns" { clk clk~out0 Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out RSDecoder:inst1|fifo_decode:fifo_decode|wordstart RSDecoder:inst1|Dec2Bit:Dec2Bit|enable } { 0.000ns 0.000ns 0.745ns 0.534ns 3.457ns 0.542ns 3.826ns 1.351ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.972 ns - Longest register register " "Info: - Longest register to register delay is 1.972 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RSDecoder:inst1\|Dec2Bit:Dec2Bit\|enable 1 REG LC_X19_Y11_N5 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X19_Y11_N5; Fanout = 6; REG Node = 'RSDecoder:inst1\|Dec2Bit:Dec2Bit\|enable'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { RSDecoder:inst1|Dec2Bit:Dec2Bit|enable } "NODE_NAME" } "" } } { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.526 ns) + CELL(0.114 ns) 0.640 ns RSDecoder:inst1\|Dec2Bit:Dec2Bit\|buff\[4\]~5 2 COMB LC_X19_Y11_N7 5 " "Info: 2: + IC(0.526 ns) + CELL(0.114 ns) = 0.640 ns; Loc. = LC_X19_Y11_N7; Fanout = 5; COMB Node = 'RSDecoder:inst1\|Dec2Bit:Dec2Bit\|buff\[4\]~5'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "0.640 ns" { RSDecoder:inst1|Dec2Bit:Dec2Bit|enable RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[4]~5 } "NODE_NAME" } "" } } { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.465 ns) + CELL(0.867 ns) 1.972 ns RSDecoder:inst1\|Dec2Bit:Dec2Bit\|buff\[0\] 3 REG LC_X19_Y11_N3 2 " "Info: 3: + IC(0.465 ns) + CELL(0.867 ns) = 1.972 ns; Loc. = LC_X19_Y11_N3; Fanout = 2; REG Node = 'RSDecoder:inst1\|Dec2Bit:Dec2Bit\|buff\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "1.332 ns" { RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[4]~5 RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0] } "NODE_NAME" } "" } } { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.981 ns ( 49.75 % ) " "Info: Total cell delay = 0.981 ns ( 49.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.991 ns ( 50.25 % ) " "Info: Total interconnect delay = 0.991 ns ( 50.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "1.972 ns" { RSDecoder:inst1|Dec2Bit:Dec2Bit|enable RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[4]~5 RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.972 ns" { RSDecoder:inst1|Dec2Bit:Dec2Bit|enable RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[4]~5 RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0] } { 0.000ns 0.526ns 0.465ns } { 0.000ns 0.114ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "7.713 ns" { clk Clock:inst3|divide3:divideb|clk_temp2 Clock:inst3|divide3:divideb|clk_out RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.713 ns" { clk clk~out0 Clock:inst3|divide3:divideb|clk_temp2 Clock:inst3|divide3:divideb|clk_out RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0] } { 0.000ns 0.000ns 0.745ns 0.000ns 3.475ns } { 0.000ns 1.469ns 0.935ns 0.378ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "15.668 ns" { clk Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out RSDecoder:inst1|fifo_decode:fifo_decode|wordstart RSDecoder:inst1|Dec2Bit:Dec2Bit|enable } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "15.668 ns" { clk clk~out0 Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out RSDecoder:inst1|fifo_decode:fifo_decode|wordstart RSDecoder:inst1|Dec2Bit:Dec2Bit|enable } { 0.000ns 0.000ns 0.745ns 0.534ns 3.457ns 0.542ns 3.826ns 1.351ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns 0.935ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "1.972 ns" { RSDecoder:inst1|Dec2Bit:Dec2Bit|enable RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[4]~5 RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "1.972 ns" { RSDecoder:inst1|Dec2Bit:Dec2Bit|enable RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[4]~5 RSDecoder:inst1|Dec2Bit:Dec2Bit|buff[0] } { 0.000ns 0.526ns 0.465ns } { 0.000ns 0.114ns 0.867ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'clk' 163 " "Warning: Can't achieve timing requirement Clock Setup: 'clk' along 163 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0 register RSDecoder:inst1\|Bit2Dec:Bit2Dec\|out\[4\] memory RSDecoder:inst1\|lpm_ram_dp0:ram1\|altsyncram:altsyncram_component\|altsyncram_lva1:auto_generated\|ram_block1a3~porta_datain_reg4 -3.147 ns " "Info: Minimum slack time is -3.147 ns for clock \"Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0\" between source register \"RSDecoder:inst1\|Bit2Dec:Bit2Dec\|out\[4\]\" and destination memory \"RSDecoder:inst1\|lpm_ram_dp0:ram1\|altsyncram:altsyncram_component\|altsyncram_lva1:auto_generated\|ram_block1a3~porta_datain_reg4\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.781 ns + Shortest register memory " "Info: + Shortest register to memory delay is 1.781 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RSDecoder:inst1\|Bit2Dec:Bit2Dec\|out\[4\] 1 REG LC_X15_Y12_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y12_N6; Fanout = 1; REG Node = 'RSDecoder:inst1\|Bit2Dec:Bit2Dec\|out\[4\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { RSDecoder:inst1|Bit2Dec:Bit2Dec|out[4] } "NODE_NAME" } "" } } { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.425 ns) + CELL(0.356 ns) 1.781 ns RSDecoder:inst1\|lpm_ram_dp0:ram1\|altsyncram:altsyncram_component\|altsyncram_lva1:auto_generated\|ram_block1a3~porta_datain_reg4 2 MEM M4K_X17_Y12 1 " "Info: 2: + IC(1.425 ns) + CELL(0.356 ns) = 1.781 ns; Loc. = M4K_X17_Y12; Fanout = 1; MEM Node = 'RSDecoder:inst1\|lpm_ram_dp0:ram1\|altsyncram:altsyncram_component\|altsyncram_lva1:auto_generated\|ram_block1a3~porta_datain_reg4'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_en