top.tan.qmsg

RS编码的verilog源代码

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0 register RSEncoder:inst\|fifo_encode:B\|temp\[0\] register RSEncoder:inst\|fifo_encode:B\|rdclocken -9.142 ns " "Info: Slack time is -9.142 ns for clock \"Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0\" between source register \"RSEncoder:inst\|fifo_encode:B\|temp\[0\]\" and destination register \"RSEncoder:inst\|fifo_encode:B\|rdclocken\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-5.996 ns + Largest register register " "Info: + Largest register to register requirement is -5.996 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "0.479 ns + " "Info: + Setup relationship between source and destination is 0.479 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.479 ns " "Info: + Latch edge is 0.479 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0 27.224 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0\" is 27.224 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 14.796 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 14.796 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.214 ns + Largest " "Info: + Largest clock skew is -6.214 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0 destination 7.198 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0\" to destination register is 7.198 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0 1 CLK PLL_2 40 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 40; CLK Node = 'Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 765 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.935 ns) 2.609 ns RSEncoder:inst\|divide5:divideb\|clk_temp2 2 REG LC_X27_Y10_N2 1 " "Info: 2: + IC(1.674 ns) + CELL(0.935 ns) = 2.609 ns; Loc. = LC_X27_Y10_N2; Fanout = 1; REG Node = 'RSEncoder:inst\|divide5:divideb\|clk_temp2'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "2.609 ns" { Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 RSEncoder:inst|divide5:divideb|clk_temp2 } "NODE_NAME" } "" } } { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.378 ns) 2.987 ns RSEncoder:inst\|divide5:divideb\|clk_out 3 COMB LC_X27_Y10_N2 105 " "Info: 3: + IC(0.000 ns) + CELL(0.378 ns) = 2.987 ns; Loc. = LC_X27_Y10_N2; Fanout = 105; COMB Node = 'RSEncoder:inst\|divide5:divideb\|clk_out'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "0.378 ns" { RSEncoder:inst|divide5:divideb|clk_temp2 RSEncoder:inst|divide5:divideb|clk_out } "NODE_NAME" } "" } } { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.711 ns) 7.198 ns RSEncoder:inst\|fifo_encode:B\|rdclocken 4 REG LC_X12_Y14_N6 10 " "Info: 4: + IC(3.500 ns) + CELL(0.711 ns) = 7.198 ns; Loc. = LC_X12_Y14_N6; Fanout = 10; REG Node = 'RSEncoder:inst\|fifo_encode:B\|rdclocken'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "4.211 ns" { RSEncoder:inst|divide5:divideb|clk_out RSEncoder:inst|fifo_encode:B|rdclocken } "NODE_NAME" } "" } } { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.024 ns ( 28.12 % ) " "Info: Total cell delay = 2.024 ns ( 28.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.174 ns ( 71.88 % ) " "Info: Total interconnect delay = 5.174 ns ( 71.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "7.198 ns" { Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 RSEncoder:inst|divide5:divideb|clk_temp2 RSEncoder:inst|divide5:divideb|clk_out RSEncoder:inst|fifo_encode:B|rdclocken } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.198 ns" { Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 RSEncoder:inst|divide5:divideb|clk_temp2 RSEncoder:inst|divide5:divideb|clk_out RSEncoder:inst|fifo_encode:B|rdclocken } { 0.000ns 1.674ns 0.000ns 3.500ns } { 0.000ns 0.935ns 0.378ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 13.412 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 13.412 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_153 11 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 11; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { clk } "NODE_NAME" } "" } } { "rs.bdf" "" { Schematic "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rs.bdf" { { 112 -144 24 128 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns Clock:inst3\|divide3:divideb\|clk_temp1 2 REG LC_X8_Y10_N3 3 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N3; Fanout = 3; REG Node = 'Clock:inst3\|divide3:divideb\|clk_temp1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "1.680 ns" { clk Clock:inst3|divide3:divideb|clk_temp1 } "NODE_NAME" } "" } } { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.114 ns) 3.797 ns Clock:inst3\|divide3:divideb\|clk_out 3 COMB LC_X8_Y10_N9 39 " "Info: 3: + IC(0.534 ns) + CELL(0.114 ns) = 3.797 ns; Loc. = LC_X8_Y10_N9; Fanout = 39; COMB Node = 'Clock:inst3\|divide3:divideb\|clk_out'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "0.648 ns" { Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out } "NODE_NAME" } "" } } { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.457 ns) + CELL(0.935 ns) 8.189 ns RSEncoder:inst\|divide5:dividea\|clk_temp1 4 REG LC_X10_Y10_N0 3 " "Info: 4: + IC(3.457 ns) + CELL(0.935 ns) = 8.189 ns; Loc. = LC_X10_Y10_N0; Fanout = 3; REG Node = 'RSEncoder:inst\|divide5:dividea\|clk_temp1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "4.392 ns" { Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 } "NODE_NAME" } "" } } { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.114 ns) 8.845 ns RSDecoder:inst1\|divide5:dividea\|clk_out 5 COMB LC_X10_Y10_N2 44 " "Info: 5: + IC(0.542 ns) + CELL(0.114 ns) = 8.845 ns; Loc. = LC_X10_Y10_N2; Fanout = 44; COMB Node = 'RSDecoder:inst1\|divide5:dividea\|clk_out'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "0.656 ns" { RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out } "NODE_NAME" } "" } } { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.856 ns) + CELL(0.711 ns) 13.412 ns RSEncoder:inst\|fifo_encode:B\|temp\[0\] 6 REG LC_X11_Y14_N5 4 " "Info: 6: + IC(3.856 ns) + CELL(0.711 ns) = 13.412 ns; Loc. = LC_X11_Y14_N5; Fanout = 4; REG Node = 'RSEncoder:inst\|fifo_encode:B\|temp\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "4.567 ns" { RSDecoder:inst1|divide5:dividea|clk_out RSEncoder:inst|fifo_encode:B|temp[0] } "NODE_NAME" } "" } } { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.278 ns ( 31.90 % ) " "Info: Total cell delay = 4.278 ns ( 31.90 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.134 ns ( 68.10 % ) " "Info: Total interconnect delay = 9.134 ns ( 68.10 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "13.412 ns" { clk Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out RSEncoder:inst|fifo_encode:B|temp[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.412 ns" { clk clk~out0 Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out RSEncoder:inst|fifo_encode:B|temp[0] } { 0.000ns 0.000ns 0.745ns 0.534ns 3.457ns 0.542ns 3.856ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "7.198 ns" { Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 RSEncoder:inst|divide5:divideb|clk_temp2 RSEncoder:inst|divide5:divideb|clk_out RSEncoder:inst|fifo_encode:B|rdclocken } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.198 ns" { Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 RSEncoder:inst|divide5:divideb|clk_temp2 RSEncoder:inst|divide5:divideb|clk_out RSEncoder:inst|fifo_encode:B|rdclocken } { 0.000ns 1.674ns 0.000ns 3.500ns } { 0.000ns 0.935ns 0.378ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "13.412 ns" { clk Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out RSEncoder:inst|fifo_encode:B|temp[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.412 ns" { clk clk~out0 Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out RSEncoder:inst|fifo_encode:B|temp[0] } { 0.000ns 0.000ns 0.745ns 0.534ns 3.457ns 0.542ns 3.856ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 28 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "7.198 ns" { Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 RSEncoder:inst|divide5:divideb|clk_temp2 RSEncoder:inst|divide5:divideb|clk_out RSEncoder:inst|fifo_encode:B|rdclocken } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.198 ns" { Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 RSEncoder:inst|divide5:divideb|clk_temp2 RSEncoder:inst|divide5:divideb|clk_out RSEncoder:inst|fifo_encode:B|rdclocken } { 0.000ns 1.674ns 0.000ns 3.500ns } { 0.000ns 0.935ns 0.378ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "13.412 ns" { clk Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out RSEncoder:inst|fifo_encode:B|temp[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.412 ns" { clk clk~out0 Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out RSEncoder:inst|fifo_encode:B|temp[0] } { 0.000ns 0.000ns 0.745ns 0.534ns 3.457ns 0.542ns 3.856ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns 0.711ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.146 ns - Longest register register " "Info: - Longest register to register delay is 3.146 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RSEncoder:inst\|fifo_encode:B\|temp\[0\] 1 REG LC_X11_Y14_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y14_N5; Fanout = 4; REG Node = 'RSEncoder:inst\|fifo_encode:B\|temp\[0\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "" { RSEncoder:inst|fifo_encode:B|temp[0] } "NODE_NAME" } "" } } { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.515 ns) + CELL(0.442 ns) 0.957 ns RSEncoder:inst\|fifo_encode:B\|always2~296 2 COMB LC_X11_Y14_N4 1 " "Info: 2: + IC(0.515 ns) + CELL(0.442 ns) = 0.957 ns; Loc. = LC_X11_Y14_N4; Fanout = 1; COMB Node = 'RSEncoder:inst\|fifo_encode:B\|always2~296'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "0.957 ns" { RSEncoder:inst|fifo_encode:B|temp[0] RSEncoder:inst|fifo_encode:B|always2~296 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.736 ns) + CELL(0.114 ns) 1.807 ns RSEncoder:inst\|fifo_encode:B\|always2~0 3 COMB LC_X12_Y14_N9 8 " "Info: 3: + IC(0.736 ns) + CELL(0.114 ns) = 1.807 ns; Loc. = LC_X12_Y14_N9; Fanout = 8; COMB Node = 'RSEncoder:inst\|fifo_encode:B\|always2~0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "0.850 ns" { RSEncoder:inst|fifo_encode:B|always2~296 RSEncoder:inst|fifo_encode:B|always2~0 } "NODE_NAME" } "" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.867 ns) 3.146 ns RSEncoder:inst\|fifo_encode:B\|rdclocken 4 REG LC_X12_Y14_N6 10 " "Info: 4: + IC(0.472 ns) + CELL(0.867 ns) = 3.146 ns; Loc. = LC_X12_Y14_N6; Fanout = 10; REG Node = 'RSEncoder:inst\|fifo_encode:B\|rdclocken'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "1.339 ns" { RSEncoder:inst|fifo_encode:B|always2~0 RSEncoder:inst|fifo_encode:B|rdclocken } "NODE_NAME" } "" } } { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.423 ns ( 45.23 % ) " "Info: Total cell delay = 1.423 ns ( 45.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.723 ns ( 54.77 % ) " "Info: Total interconnect delay = 1.723 ns ( 54.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "3.146 ns" { RSEncoder:inst|fifo_encode:B|temp[0] RSEncoder:inst|fifo_encode:B|always2~296 RSEncoder:inst|fifo_encode:B|always2~0 RSEncoder:inst|fifo_encode:B|rdclocken } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.146 ns" { RSEncoder:inst|fifo_encode:B|temp[0] RSEncoder:inst|fifo_encode:B|always2~296 RSEncoder:inst|fifo_encode:B|always2~0 RSEncoder:inst|fifo_encode:B|rdclocken } { 0.000ns 0.515ns 0.736ns 0.472ns } { 0.000ns 0.442ns 0.114ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "7.198 ns" { Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 RSEncoder:inst|divide5:divideb|clk_temp2 RSEncoder:inst|divide5:divideb|clk_out RSEncoder:inst|fifo_encode:B|rdclocken } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.198 ns" { Clock:inst3|pll:p31_57|altpll:altpll_component|_clk0 RSEncoder:inst|divide5:divideb|clk_temp2 RSEncoder:inst|divide5:divideb|clk_out RSEncoder:inst|fifo_encode:B|rdclocken } { 0.000ns 1.674ns 0.000ns 3.500ns } { 0.000ns 0.935ns 0.378ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "13.412 ns" { clk Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out RSEncoder:inst|fifo_encode:B|temp[0] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "13.412 ns" { clk clk~out0 Clock:inst3|divide3:divideb|clk_temp1 Clock:inst3|divide3:divideb|clk_out RSEncoder:inst|divide5:dividea|clk_temp1 RSDecoder:inst1|divide5:dividea|clk_out RSEncoder:inst|fifo_encode:B|temp[0] } { 0.000ns 0.000ns 0.745ns 0.534ns 3.457ns 0.542ns 3.856ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.935ns 0.114ns 0.711ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "top" "UNKNOWN" "V1" "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/db/RS_encode_and_decode.quartus_db" { Floorplan "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/" "" "3.146 ns" { RSEncoder:inst|fifo_encode:B|temp[0] RSEncoder:inst|fifo_encode:B|always2~296 RSEncoder:inst|fifo_encode:B|always2~0 RSEncoder:inst|fifo_encode:B|rdclocken } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.146 ns" { RSEncoder:inst|fifo_encode:B|temp[0] RSEncoder:inst|fifo_encode:B|always2~296 RSEncoder:inst|fifo_encode:B|always2~0 RSEncoder:inst|fifo_encode:B|rdclocken } { 0.000ns 0.515ns 0.736ns 0.472ns } { 0.000ns 0.442ns 0.114ns 0.867ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0' 48 " "Warning: Can't achieve timing requirement Clock Setup: 'Clock:inst3\|pll:p31_57\|altpll:altpll_component\|_clk0' along 48 path(s). See Report window for details." {  } {  } 0 0 "Can't achieve timing requirement %1!s! along %2!d! path(s). See Report window for details." 0 0}