top.tan.qmsg

RS编码的verilog源代码

{ "Warning" "WTAN_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTAN_COMB_LATCH_NODE" "RSDecoder:inst1\|fifo_decode:fifo_decode\|isword1 " "Warning: Node \"RSDecoder:inst1\|fifo_decode:fifo_decode\|isword1\" is a latch" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 98 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}
{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "18 " "Warning: Found 18 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "inst18 " "Info: Detected ripple clock \"inst18\" as buffer" {  } { { "rs.bdf" "" { Schematic "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rs.bdf" { { 280 816 880 360 "inst18" "" } } } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "inst18" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "RSDecoder:inst1\|Bit2Dec:Bit2Dec\|outstart " "Info: Detected ripple clock \"RSDecoder:inst1\|Bit2Dec:Bit2Dec\|outstart\" as buffer" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 54 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSDecoder:inst1\|Bit2Dec:Bit2Dec\|outstart" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "RSEncoder:inst\|Bit2Dec:A\|outstart " "Info: Detected ripple clock \"RSEncoder:inst\|Bit2Dec:A\|outstart\" as buffer" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 54 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSEncoder:inst\|Bit2Dec:A\|outstart" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "RSEncoder:inst\|fifo_encode:B\|wordstart " "Info: Detected ripple clock \"RSEncoder:inst\|fifo_encode:B\|wordstart\" as buffer" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 13 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSEncoder:inst\|fifo_encode:B\|wordstart" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "RSEncoder:inst\|divide5:divideb\|clk_temp2 " "Info: Detected ripple clock \"RSEncoder:inst\|divide5:divideb\|clk_temp2\" as buffer" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSEncoder:inst\|divide5:divideb\|clk_temp2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "RSEncoder:inst\|divide5:divideb\|clk_temp1 " "Info: Detected ripple clock \"RSEncoder:inst\|divide5:divideb\|clk_temp1\" as buffer" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 6 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSEncoder:inst\|divide5:divideb\|clk_temp1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "RSEncoder:inst\|divide5:divideb\|clk_out " "Info: Detected gated clock \"RSEncoder:inst\|divide5:divideb\|clk_out\" as buffer" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSEncoder:inst\|divide5:divideb\|clk_out" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "RSEncoder:inst\|divide5:dividea\|clk_temp2 " "Info: Detected ripple clock \"RSEncoder:inst\|divide5:dividea\|clk_temp2\" as buffer" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSEncoder:inst\|divide5:dividea\|clk_temp2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "RSEncoder:inst\|divide5:dividea\|clk_temp1 " "Info: Detected ripple clock \"RSEncoder:inst\|divide5:dividea\|clk_temp1\" as buffer" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 6 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSEncoder:inst\|divide5:dividea\|clk_temp1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "RSDecoder:inst1\|divide5:dividea\|clk_out " "Info: Detected gated clock \"RSDecoder:inst1\|divide5:dividea\|clk_out\" as buffer" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSDecoder:inst1\|divide5:dividea\|clk_out" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "nrz:inst2\|datastart " "Info: Detected ripple clock \"nrz:inst2\|datastart\" as buffer" {  } { { "source_nrz.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/source_nrz.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "nrz:inst2\|datastart" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "RSDecoder:inst1\|divide5:dividec\|clk_temp2 " "Info: Detected ripple clock \"RSDecoder:inst1\|divide5:dividec\|clk_temp2\" as buffer" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 7 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSDecoder:inst1\|divide5:dividec\|clk_temp2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "RSDecoder:inst1\|divide5:dividec\|clk_temp1 " "Info: Detected ripple clock \"RSDecoder:inst1\|divide5:dividec\|clk_temp1\" as buffer" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 6 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSDecoder:inst1\|divide5:dividec\|clk_temp1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "RSDecoder:inst1\|divide5:dividec\|clk_out " "Info: Detected gated clock \"RSDecoder:inst1\|divide5:dividec\|clk_out\" as buffer" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 4 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSDecoder:inst1\|divide5:dividec\|clk_out" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "Clock:inst3\|divide3:divideb\|clk_temp2 " "Info: Detected ripple clock \"Clock:inst3\|divide3:divideb\|clk_temp2\" as buffer" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 46 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Clock:inst3\|divide3:divideb\|clk_temp2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "Clock:inst3\|divide3:divideb\|clk_temp1 " "Info: Detected ripple clock \"Clock:inst3\|divide3:divideb\|clk_temp1\" as buffer" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 45 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Clock:inst3\|divide3:divideb\|clk_temp1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "RSDecoder:inst1\|fifo_decode:fifo_decode\|wordstart " "Info: Detected ripple clock \"RSDecoder:inst1\|fifo_decode:fifo_decode\|wordstart\" as buffer" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 97 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "RSDecoder:inst1\|fifo_decode:fifo_decode\|wordstart" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "Clock:inst3\|divide3:divideb\|clk_out " "Info: Detected gated clock \"Clock:inst3\|divide3:divideb\|clk_out\" as buffer" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 43 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "Clock:inst3\|divide3:divideb\|clk_out" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}