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RS编码的verilog源代码

load => load~0.IN2
init => init~0.IN2
hold => hold~0.IN2
iter_control => iter_control~0.IN1
delta_cflex_out[0] <= register_pe:reg1.port2
delta_cflex_out[1] <= register_pe:reg1.port2
delta_cflex_out[2] <= register_pe:reg1.port2
delta_cflex_out[3] <= register_pe:reg1.port2
delta_cflex_out[4] <= register_pe:reg1.port2


|rs|RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE1|lcpmult:multiplier1
in1[4] => intvald~12.IN0
in1[4] => intvale~0.IN0
in1[4] => intvale~6.IN0
in1[4] => intvale~10.IN0
in1[4] => intvale[3].IN0
in1[3] => intvald~6.IN1
in1[3] => intvald~13.IN0
in1[3] => intvale~1.IN0
in1[3] => intvale~7.IN0
in1[3] => intvale~11.IN0
in1[2] => intvald~2.IN1
in1[2] => intvald~7.IN1
in1[2] => intvald~15.IN0
in1[2] => intvale~3.IN0
in1[2] => intvale~9.IN0
in1[1] => intvald~0.IN1
in1[1] => intvald~3.IN1
in1[1] => intvald~9.IN1
in1[1] => intvald~17.IN0
in1[1] => intvale~4.IN0
in1[0] => intvald[0].IN1
in1[0] => intvald~1.IN1
in1[0] => intvald~4.IN1
in1[0] => intvald~10.IN1
in1[0] => intvald~18.IN0
in2[4] => intvald~18.IN1
in2[4] => intvale~4.IN1
in2[4] => intvale~9.IN1
in2[4] => intvale~11.IN1
in2[4] => intvale[3].IN1
in2[3] => intvald~10.IN0
in2[3] => intvald~17.IN1
in2[3] => intvale~3.IN1
in2[3] => intvale~7.IN1
in2[3] => intvale~10.IN1
in2[2] => intvald~4.IN0
in2[2] => intvald~9.IN0
in2[2] => intvald~15.IN1
in2[2] => intvale~1.IN1
in2[2] => intvale~6.IN1
in2[1] => intvald~1.IN0
in2[1] => intvald~3.IN0
in2[1] => intvald~7.IN0
in2[1] => intvald~13.IN1
in2[1] => intvale~0.IN1
in2[0] => intvald[0].IN0
in2[0] => intvald~0.IN0
in2[0] => intvald~2.IN0
in2[0] => intvald~6.IN0
in2[0] => intvald~12.IN1
out[4] <= out~6.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out~5.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out~3.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[0] <= out~0.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE1|lcpmult:multiplier2
in1[4] => intvald~12.IN0
in1[4] => intvale~0.IN0
in1[4] => intvale~6.IN0
in1[4] => intvale~10.IN0
in1[4] => intvale[3].IN0
in1[3] => intvald~6.IN1
in1[3] => intvald~13.IN0
in1[3] => intvale~1.IN0
in1[3] => intvale~7.IN0
in1[3] => intvale~11.IN0
in1[2] => intvald~2.IN1
in1[2] => intvald~7.IN1
in1[2] => intvald~15.IN0
in1[2] => intvale~3.IN0
in1[2] => intvale~9.IN0
in1[1] => intvald~0.IN1
in1[1] => intvald~3.IN1
in1[1] => intvald~9.IN1
in1[1] => intvald~17.IN0
in1[1] => intvale~4.IN0
in1[0] => intvald[0].IN1
in1[0] => intvald~1.IN1
in1[0] => intvald~4.IN1
in1[0] => intvald~10.IN1
in1[0] => intvald~18.IN0
in2[4] => intvald~18.IN1
in2[4] => intvale~4.IN1
in2[4] => intvale~9.IN1
in2[4] => intvale~11.IN1
in2[4] => intvale[3].IN1
in2[3] => intvald~10.IN0
in2[3] => intvald~17.IN1
in2[3] => intvale~3.IN1
in2[3] => intvale~7.IN1
in2[3] => intvale~10.IN1
in2[2] => intvald~4.IN0
in2[2] => intvald~9.IN0
in2[2] => intvald~15.IN1
in2[2] => intvale~1.IN1
in2[2] => intvale~6.IN1
in2[1] => intvald~1.IN0
in2[1] => intvald~3.IN0
in2[1] => intvald~7.IN0
in2[1] => intvald~13.IN1
in2[1] => intvale~0.IN1
in2[0] => intvald[0].IN0
in2[0] => intvald~0.IN0
in2[0] => intvald~2.IN0
in2[0] => intvald~6.IN0
in2[0] => intvald~12.IN1
out[4] <= out~6.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out~5.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out~3.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[0] <= out~0.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE1|register_pe:reg1
datain[0] => out~9.DATAB
datain[1] => out~8.DATAB
datain[2] => out~7.DATAB
datain[3] => out~6.DATAB
datain[4] => out~5.DATAB
initdata[0] => out~14.DATAB
initdata[1] => out~13.DATAB
initdata[2] => out~12.DATAB
initdata[3] => out~11.DATAB
initdata[4] => out~10.DATAB
dataout[0] <= out[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= out[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= out[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= out[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= out[4].DB_MAX_OUTPUT_PORT_TYPE
load => out~5.OUTPUTSELECT
load => out~6.OUTPUTSELECT
load => out~7.OUTPUTSELECT
load => out~8.OUTPUTSELECT
load => out~9.OUTPUTSELECT
initialize => out~10.OUTPUTSELECT
initialize => out~11.OUTPUTSELECT
initialize => out~12.OUTPUTSELECT
initialize => out~13.OUTPUTSELECT
initialize => out~14.OUTPUTSELECT
hold => out~0.OUTPUTSELECT
hold => out~1.OUTPUTSELECT
hold => out~2.OUTPUTSELECT
hold => out~3.OUTPUTSELECT
hold => out~4.OUTPUTSELECT
clock => out[3].CLK
clock => out[2].CLK
clock => out[1].CLK
clock => out[0].CLK
clock => out[4].CLK


|rs|RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE1|register_pe:reg2
datain[0] => out~9.DATAB
datain[1] => out~8.DATAB
datain[2] => out~7.DATAB
datain[3] => out~6.DATAB
datain[4] => out~5.DATAB
initdata[0] => out~14.DATAB
initdata[1] => out~13.DATAB
initdata[2] => out~12.DATAB
initdata[3] => out~11.DATAB
initdata[4] => out~10.DATAB
dataout[0] <= out[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= out[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= out[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= out[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= out[4].DB_MAX_OUTPUT_PORT_TYPE
load => out~5.OUTPUTSELECT
load => out~6.OUTPUTSELECT
load => out~7.OUTPUTSELECT
load => out~8.OUTPUTSELECT
load => out~9.OUTPUTSELECT
initialize => out~10.OUTPUTSELECT
initialize => out~11.OUTPUTSELECT
initialize => out~12.OUTPUTSELECT
initialize => out~13.OUTPUTSELECT
initialize => out~14.OUTPUTSELECT
hold => out~0.OUTPUTSELECT
hold => out~1.OUTPUTSELECT
hold => out~2.OUTPUTSELECT
hold => out~3.OUTPUTSELECT
hold => out~4.OUTPUTSELECT
clock => out[3].CLK
clock => out[2].CLK
clock => out[1].CLK
clock => out[0].CLK
clock => out[4].CLK


|rs|RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE1|mux2_to_1:multiplexer
in1[0] => out~4.DATAA
in1[1] => out~3.DATAA
in1[2] => out~2.DATAA
in1[3] => out~1.DATAA
in1[4] => out~0.DATAA
in2[0] => out~4.DATAB
in2[1] => out~3.DATAB
in2[2] => out~2.DATAB
in2[3] => out~1.DATAB
in2[4] => out~0.DATAB
out[0] <= out~4.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~3.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out~2.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= out~0.DB_MAX_OUTPUT_PORT_TYPE
sel => Decoder~0.IN0


|rs|RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE2
delta_cflex_in[0] => delta_cflex_in[0]~4.IN2
delta_cflex_in[1] => delta_cflex_in[1]~3.IN2
delta_cflex_in[2] => delta_cflex_in[2]~2.IN2
delta_cflex_in[3] => delta_cflex_in[3]~1.IN2
delta_cflex_in[4] => delta_cflex_in[4]~0.IN2
syndval[0] => syndval[0]~4.IN2
syndval[1] => syndval[1]~3.IN2
syndval[2] => syndval[2]~2.IN2
syndval[3] => syndval[3]~1.IN2
syndval[4] => syndval[4]~0.IN2
gamma[0] => gamma[0]~4.IN1
gamma[1] => gamma[1]~3.IN1
gamma[2] => gamma[2]~2.IN1
gamma[3] => gamma[3]~1.IN1
gamma[4] => gamma[4]~0.IN1
delta[0] => delta[0]~4.IN1
delta[1] => delta[1]~3.IN1
delta[2] => delta[2]~2.IN1
delta[3] => delta[3]~1.IN1
delta[4] => delta[4]~0.IN1
clock => clock~0.IN2
load => load~0.IN2
init => init~0.IN2
hold => hold~0.IN2
iter_control => iter_control~0.IN1
delta_cflex_out[0] <= register_pe:reg1.port2
delta_cflex_out[1] <= register_pe:reg1.port2
delta_cflex_out[2] <= register_pe:reg1.port2
delta_cflex_out[3] <= register_pe:reg1.port2
delta_cflex_out[4] <= register_pe:reg1.port2


|rs|RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE2|lcpmult:multiplier1
in1[4] => intvald~12.IN0
in1[4] => intvale~0.IN0
in1[4] => intvale~6.IN0
in1[4] => intvale~10.IN0
in1[4] => intvale[3].IN0
in1[3] => intvald~6.IN1
in1[3] => intvald~13.IN0
in1[3] => intvale~1.IN0
in1[3] => intvale~7.IN0
in1[3] => intvale~11.IN0
in1[2] => intvald~2.IN1
in1[2] => intvald~7.IN1
in1[2] => intvald~15.IN0
in1[2] => intvale~3.IN0
in1[2] => intvale~9.IN0
in1[1] => intvald~0.IN1
in1[1] => intvald~3.IN1
in1[1] => intvald~9.IN1
in1[1] => intvald~17.IN0
in1[1] => intvale~4.IN0
in1[0] => intvald[0].IN1
in1[0] => intvald~1.IN1
in1[0] => intvald~4.IN1
in1[0] => intvald~10.IN1
in1[0] => intvald~18.IN0
in2[4] => intvald~18.IN1
in2[4] => intvale~4.IN1
in2[4] => intvale~9.IN1
in2[4] => intvale~11.IN1
in2[4] => intvale[3].IN1
in2[3] => intvald~10.IN0
in2[3] => intvald~17.IN1
in2[3] => intvale~3.IN1
in2[3] => intvale~7.IN1
in2[3] => intvale~10.IN1
in2[2] => intvald~4.IN0
in2[2] => intvald~9.IN0
in2[2] => intvald~15.IN1
in2[2] => intvale~1.IN1
in2[2] => intvale~6.IN1
in2[1] => intvald~1.IN0
in2[1] => intvald~3.IN0
in2[1] => intvald~7.IN0
in2[1] => intvald~13.IN1
in2[1] => intvale~0.IN1
in2[0] => intvald[0].IN0
in2[0] => intvald~0.IN0
in2[0] => intvald~2.IN0
in2[0] => intvald~6.IN0
in2[0] => intvald~12.IN1
out[4] <= out~6.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out~5.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out~3.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[0] <= out~0.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE2|lcpmult:multiplier2
in1[4] => intvald~12.IN0
in1[4] => intvale~0.IN0
in1[4] => intvale~6.IN0
in1[4] => intvale~10.IN0
in1[4] => intvale[3].IN0
in1[3] => intvald~6.IN1
in1[3] => intvald~13.IN0
in1[3] => intvale~1.IN0
in1[3] => intvale~7.IN0
in1[3] => intvale~11.IN0
in1[2] => intvald~2.IN1
in1[2] => intvald~7.IN1
in1[2] => intvald~15.IN0
in1[2] => intvale~3.IN0
in1[2] => intvale~9.IN0
in1[1] => intvald~0.IN1
in1[1] => intvald~3.IN1
in1[1] => intvald~9.IN1
in1[1] => intvald~17.IN0
in1[1] => intvale~4.IN0
in1[0] => intvald[0].IN1
in1[0] => intvald~1.IN1
in1[0] => intvald~4.IN1
in1[0] => intvald~10.IN1
in1[0] => intvald~18.IN0
in2[4] => intvald~18.IN1
in2[4] => intvale~4.IN1
in2[4] => intvale~9.IN1
in2[4] => intvale~11.IN1
in2[4] => intvale[3].IN1
in2[3] => intvald~10.IN0
in2[3] => intvald~17.IN1
in2[3] => intvale~3.IN1
in2[3] => intvale~7.IN1
in2[3] => intvale~10.IN1
in2[2] => intvald~4.IN0
in2[2] => intvald~9.IN0
in2[2] => intvald~15.IN1
in2[2] => intvale~1.IN1
in2[2] => intvale~6.IN1
in2[1] => intvald~1.IN0
in2[1] => intvald~3.IN0
in2[1] => intvald~7.IN0
in2[1] => intvald~13.IN1
in2[1] => intvale~0.IN1
in2[0] => intvald[0].IN0
in2[0] => intvald~0.IN0
in2[0] => intvald~2.IN0
in2[0] => intvald~6.IN0
in2[0] => intvald~12.IN1
out[4] <= out~6.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out~5.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out~3.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[0] <= out~0.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|KES_block:KESblock|PE:PE2|register_pe:reg1
datain[0] => out~9.DATAB
datain[1] => out~8.DATAB
datain[2] => out~7.DATAB
datain[3] => out~6.DATAB
datain[4] => out~5.DATAB
initdata[0] => out~14.DATAB
initdata[1] => out~13.DATAB
initdata[2] => out~12.DATAB
initdata[3] => out~11.DATAB
initdata[4] => out~10.DATAB
dataout[0] <= out[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= out[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= out[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= out[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= out[4].DB_MAX_OUTPUT_PORT_TYPE
load => out~5.OUTPUTSELECT
load => out~6.OUTPUTSELECT
load => out~7.OUTPUTSELECT
load => out~8.OUTPUTSELECT
load => out~9.OUTPUTSELECT
initialize => out~10.OUTPUTSELECT
initialize => out~11.OUTPUTSELECT
initialize => out~12.OUTPUTSELECT
initialize => out~13.OUTPUTSELECT
initialize => out~14.OUTPUTSELECT
hold => out~0.OUTPUTSELECT
hold => out~1.OUTPUTSELECT
hold => out~2.OUTPUTSELECT
hold => out~3.OUTPUTSELECT
hold => out~4.OUTPUTSELECT
clock => out[3].CLK
clock => out[2].CLK
clock => out[1].CLK
clock => out[0].CLK
clock