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RS编码的verilog源代码

datain[3] => out~6.DATAB
datain[4] => out~5.DATAB
dataout[0] <= out[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= out[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= out[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= out[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= out[4].DB_MAX_OUTPUT_PORT_TYPE
load => out~5.OUTPUTSELECT
load => out~6.OUTPUTSELECT
load => out~7.OUTPUTSELECT
load => out~8.OUTPUTSELECT
load => out~9.OUTPUTSELECT
hold => out~0.OUTPUTSELECT
hold => out~1.OUTPUTSELECT
hold => out~2.OUTPUTSELECT
hold => out~3.OUTPUTSELECT
hold => out~4.OUTPUTSELECT
clock => out[3].CLK
clock => out[2].CLK
clock => out[1].CLK
clock => out[0].CLK
clock => out[4].CLK


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|gfadder:adder
in1[4] => out~0.IN0
in1[3] => out~1.IN0
in1[2] => out~2.IN0
in1[1] => out~3.IN0
in1[0] => out~4.IN0
in2[4] => out~0.IN1
in2[3] => out~1.IN1
in2[2] => out~2.IN1
in2[1] => out~3.IN1
in2[0] => out~4.IN1
out[4] <= out~0.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out~2.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~3.DB_MAX_OUTPUT_PORT_TYPE
out[0] <= out~4.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6
recword[4] => recword[4]~4.IN1
recword[3] => recword[3]~3.IN1
recword[2] => recword[2]~2.IN1
recword[1] => recword[1]~1.IN1
recword[0] => recword[0]~0.IN1
clock => clock~0.IN1
enable => enable~0.IN1
hold => hold~0.IN1
synvalue6[4] <= register5_wlh:register5bit.port1
synvalue6[3] <= register5_wlh:register5bit.port1
synvalue6[2] <= register5_wlh:register5bit.port1
synvalue6[1] <= register5_wlh:register5bit.port1
synvalue6[0] <= register5_wlh:register5bit.port1


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|register5_wlh:register5bit
datain[0] => out~9.DATAB
datain[1] => out~8.DATAB
datain[2] => out~7.DATAB
datain[3] => out~6.DATAB
datain[4] => out~5.DATAB
dataout[0] <= out[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= out[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= out[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= out[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= out[4].DB_MAX_OUTPUT_PORT_TYPE
load => out~5.OUTPUTSELECT
load => out~6.OUTPUTSELECT
load => out~7.OUTPUTSELECT
load => out~8.OUTPUTSELECT
load => out~9.OUTPUTSELECT
hold => out~0.OUTPUTSELECT
hold => out~1.OUTPUTSELECT
hold => out~2.OUTPUTSELECT
hold => out~3.OUTPUTSELECT
hold => out~4.OUTPUTSELECT
clock => out[3].CLK
clock => out[2].CLK
clock => out[1].CLK
clock => out[0].CLK
clock => out[4].CLK


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_6:cell_6|gfadder:adder
in1[4] => out~0.IN0
in1[3] => out~1.IN0
in1[2] => out~2.IN0
in1[1] => out~3.IN0
in1[0] => out~4.IN0
in2[4] => out~0.IN1
in2[3] => out~1.IN1
in2[2] => out~2.IN1
in2[1] => out~3.IN1
in2[0] => out~4.IN1
out[4] <= out~0.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out~2.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~3.DB_MAX_OUTPUT_PORT_TYPE
out[0] <= out~4.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7
recword[4] => recword[4]~4.IN1
recword[3] => recword[3]~3.IN1
recword[2] => recword[2]~2.IN1
recword[1] => recword[1]~1.IN1
recword[0] => recword[0]~0.IN1
clock => clock~0.IN1
enable => enable~0.IN1
hold => hold~0.IN1
synvalue7[4] <= register5_wlh:register5bit.port1
synvalue7[3] <= register5_wlh:register5bit.port1
synvalue7[2] <= register5_wlh:register5bit.port1
synvalue7[1] <= register5_wlh:register5bit.port1
synvalue7[0] <= register5_wlh:register5bit.port1


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|register5_wlh:register5bit
datain[0] => out~9.DATAB
datain[1] => out~8.DATAB
datain[2] => out~7.DATAB
datain[3] => out~6.DATAB
datain[4] => out~5.DATAB
dataout[0] <= out[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= out[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= out[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= out[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= out[4].DB_MAX_OUTPUT_PORT_TYPE
load => out~5.OUTPUTSELECT
load => out~6.OUTPUTSELECT
load => out~7.OUTPUTSELECT
load => out~8.OUTPUTSELECT
load => out~9.OUTPUTSELECT
hold => out~0.OUTPUTSELECT
hold => out~1.OUTPUTSELECT
hold => out~2.OUTPUTSELECT
hold => out~3.OUTPUTSELECT
hold => out~4.OUTPUTSELECT
clock => out[3].CLK
clock => out[2].CLK
clock => out[1].CLK
clock => out[0].CLK
clock => out[4].CLK


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_7:cell_7|gfadder:adder
in1[4] => out~0.IN0
in1[3] => out~1.IN0
in1[2] => out~2.IN0
in1[1] => out~3.IN0
in1[0] => out~4.IN0
in2[4] => out~0.IN1
in2[3] => out~1.IN1
in2[2] => out~2.IN1
in2[1] => out~3.IN1
in2[0] => out~4.IN1
out[4] <= out~0.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out~2.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~3.DB_MAX_OUTPUT_PORT_TYPE
out[0] <= out~4.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8
recword[4] => recword[4]~4.IN1
recword[3] => recword[3]~3.IN1
recword[2] => recword[2]~2.IN1
recword[1] => recword[1]~1.IN1
recword[0] => recword[0]~0.IN1
clock => clock~0.IN1
enable => enable~0.IN1
hold => hold~0.IN1
synvalue8[4] <= register5_wlh:register5bit.port1
synvalue8[3] <= register5_wlh:register5bit.port1
synvalue8[2] <= register5_wlh:register5bit.port1
synvalue8[1] <= outreg[1].DB_MAX_OUTPUT_PORT_TYPE
synvalue8[0] <= register5_wlh:register5bit.port1


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|register5_wlh:register5bit
datain[0] => out~9.DATAB
datain[1] => out~8.DATAB
datain[2] => out~7.DATAB
datain[3] => out~6.DATAB
datain[4] => out~5.DATAB
dataout[0] <= out[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= out[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= out[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= out[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= out[4].DB_MAX_OUTPUT_PORT_TYPE
load => out~5.OUTPUTSELECT
load => out~6.OUTPUTSELECT
load => out~7.OUTPUTSELECT
load => out~8.OUTPUTSELECT
load => out~9.OUTPUTSELECT
hold => out~0.OUTPUTSELECT
hold => out~1.OUTPUTSELECT
hold => out~2.OUTPUTSELECT
hold => out~3.OUTPUTSELECT
hold => out~4.OUTPUTSELECT
clock => out[3].CLK
clock => out[2].CLK
clock => out[1].CLK
clock => out[0].CLK
clock => out[4].CLK


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_8:cell_8|gfadder:adder
in1[4] => out~0.IN0
in1[3] => out~1.IN0
in1[2] => out~2.IN0
in1[1] => out~3.IN0
in1[0] => out~4.IN0
in2[4] => out~0.IN1
in2[3] => out~1.IN1
in2[2] => out~2.IN1
in2[1] => out~3.IN1
in2[0] => out~4.IN1
out[4] <= out~0.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out~2.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~3.DB_MAX_OUTPUT_PORT_TYPE
out[0] <= out~4.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9
recword[4] => recword[4]~4.IN1
recword[3] => recword[3]~3.IN1
recword[2] => recword[2]~2.IN1
recword[1] => recword[1]~1.IN1
recword[0] => recword[0]~0.IN1
clock => clock~0.IN1
enable => enable~0.IN1
hold => hold~0.IN1
synvalue9[4] <= register5_wlh:register5bit.port1
synvalue9[3] <= register5_wlh:register5bit.port1
synvalue9[2] <= register5_wlh:register5bit.port1
synvalue9[1] <= outreg[1].DB_MAX_OUTPUT_PORT_TYPE
synvalue9[0] <= outreg[0].DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|register5_wlh:register5bit
datain[0] => out~9.DATAB
datain[1] => out~8.DATAB
datain[2] => out~7.DATAB
datain[3] => out~6.DATAB
datain[4] => out~5.DATAB
dataout[0] <= out[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= out[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= out[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= out[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= out[4].DB_MAX_OUTPUT_PORT_TYPE
load => out~5.OUTPUTSELECT
load => out~6.OUTPUTSELECT
load => out~7.OUTPUTSELECT
load => out~8.OUTPUTSELECT
load => out~9.OUTPUTSELECT
hold => out~0.OUTPUTSELECT
hold => out~1.OUTPUTSELECT
hold => out~2.OUTPUTSELECT
hold => out~3.OUTPUTSELECT
hold => out~4.OUTPUTSELECT
clock => out[3].CLK
clock => out[2].CLK
clock => out[1].CLK
clock => out[0].CLK
clock => out[4].CLK


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_9:cell_9|gfadder:adder
in1[4] => out~0.IN0
in1[3] => out~1.IN0
in1[2] => out~2.IN0
in1[1] => out~3.IN0
in1[0] => out~4.IN0
in2[4] => out~0.IN1
in2[3] => out~1.IN1
in2[2] => out~2.IN1
in2[1] => out~3.IN1
in2[0] => out~4.IN1
out[4] <= out~0.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out~2.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~3.DB_MAX_OUTPUT_PORT_TYPE
out[0] <= out~4.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10
recword[4] => recword[4]~4.IN1
recword[3] => recword[3]~3.IN1
recword[2] => recword[2]~2.IN1
recword[1] => recword[1]~1.IN1
recword[0] => recword[0]~0.IN1
clock => clock~0.IN1
enable => enable~0.IN1
hold => hold~0.IN1
synvalue10[4] <= outreg[4].DB_MAX_OUTPUT_PORT_TYPE
synvalue10[3] <= register5_wlh:register5bit.port1
synvalue10[2] <= register5_wlh:register5bit.port1
synvalue10[1] <= outreg[1].DB_MAX_OUTPUT_PORT_TYPE
synvalue10[0] <= outreg[0].DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|register5_wlh:register5bit
datain[0] => out~9.DATAB
datain[1] => out~8.DATAB
datain[2] => out~7.DATAB
datain[3] => out~6.DATAB
datain[4] => out~5.DATAB
dataout[0] <= out[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= out[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= out[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= out[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= out[4].DB_MAX_OUTPUT_PORT_TYPE
load => out~5.OUTPUTSELECT
load => out~6.OUTPUTSELECT
load => out~7.OUTPUTSELECT
load => out~8.OUTPUTSELECT
load => out~9.OUTPUTSELECT
hold => out~0.OUTPUTSELECT
hold => out~1.OUTPUTSELECT
hold => out~2.OUTPUTSELECT
hold => out~3.OUTPUTSELECT
hold => out~4.OUTPUTSELECT
clock => out[3].CLK
clock => out[2].CLK
clock => out[1].CLK
clock => out[0].CLK
clock => out[4].CLK


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_10:cell_10|gfadder:adder
in1[4] => out~0.IN0
in1[3] => out~1.IN0
in1[2] => out~2.IN0
in1[1] => out~3.IN0
in1[0] => out~4.IN0
in2[4] => out~0.IN1
in2[3] => out~1.IN1
in2[2] => out~2.IN1
in2[1] => out~3.IN1
in2[0] => out~4.IN1
out[4] <= out~0.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out~2.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~3.DB_MAX_OUTPUT_PORT_TYPE
out[0] <= out~4.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11
recword[4] => recword[4]~4.IN1
recword[3] => recword[3]~3.IN1
recword[2] => recword[2]~2.IN1
recword[1] => recword[1]~1.IN1
recword[0] => recword[0]~0.IN1
clock => clock~0.IN1
enable => enable~0.IN1
hold => hold~0.IN1
synvalue11[4] <= outreg[4].DB_MAX_OUTPUT_PORT_TYPE
synvalue11[3] <= outreg[3].DB_MAX_OUTPUT_PORT_TYPE
synvalue11[2] <= register5_wlh:register5bit.port1
synvalue11[1] <= outreg[1].DB_MAX_OUTPUT_PORT_TYPE
synvalue11[0] <= outreg[0].DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|register5_wlh:register5bit
datain[0] => out~9.DATAB
datain[1] => out~8.DATAB
datain[2] => out~7.DATAB
datain[3] => out~6.DATAB
datain[4] => out~5.DATAB
dataout[0] <= out[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= out[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= out[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= out[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= out[4].DB_MAX_OUTPUT_PORT_TYPE
load => out~5.OUTPUTSELECT
load => out~6.OUTPUTSELECT
load => out~7.OUTPUTSELECT
load => out~8.OUTPUTSELECT
load => out~9.OUTPUTSELECT
hold => out~0.OUTPUTSELECT
hold => out~1.OUTPUTSELECT
hold => out~2.OUTPUTSELECT
hold => out~3.OUTPUTSELECT
hold => out~4.OUTPUTSELECT
clock => out[3].CLK
clock => out[2].CLK
clock => out[1].CLK
clock => out[0].CLK
clock => out[4].CLK


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_11:cell_11|gfadder:adder
in1[4] => out~0.IN0
in1[3] => out~1.IN0
in1[2] => out~2.IN0
in1[1] => out~3.IN0
in1[0] => out~4.IN0
in2[4] => out~0.IN1
in2[3] => out~1.IN1
in2[2] => out~2.IN1
in2[1] => out~3.IN1
in2[0] => out~4.IN1
out[4] <= out~0.DB_MAX_OUTPUT_PORT_TYPE