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RS编码的verilog源代码

|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock
recword[0] => recword[0]~4.IN12
recword[1] => recword[1]~3.IN12
recword[2] => recword[2]~2.IN12
recword[3] => recword[3]~1.IN12
recword[4] => recword[4]~0.IN12
clock1 => clock1~0.IN12
clock2 => state~0.IN1
active_sc => nxt_state.st1.IN2
active_sc => nxt_state.st0.IN2
reset => state~1.IN1
syndvalue0[0] <= syndcell_0:cell_0.port4
syndvalue0[1] <= syndcell_0:cell_0.port4
syndvalue0[2] <= syndcell_0:cell_0.port4
syndvalue0[3] <= syndcell_0:cell_0.port4
syndvalue0[4] <= syndcell_0:cell_0.port4
syndvalue1[0] <= syndcell_1:cell_1.port4
syndvalue1[1] <= syndcell_1:cell_1.port4
syndvalue1[2] <= syndcell_1:cell_1.port4
syndvalue1[3] <= syndcell_1:cell_1.port4
syndvalue1[4] <= syndcell_1:cell_1.port4
syndvalue2[0] <= syndcell_2:cell_2.port4
syndvalue2[1] <= syndcell_2:cell_2.port4
syndvalue2[2] <= syndcell_2:cell_2.port4
syndvalue2[3] <= syndcell_2:cell_2.port4
syndvalue2[4] <= syndcell_2:cell_2.port4
syndvalue3[0] <= syndcell_3:cell_3.port4
syndvalue3[1] <= syndcell_3:cell_3.port4
syndvalue3[2] <= syndcell_3:cell_3.port4
syndvalue3[3] <= syndcell_3:cell_3.port4
syndvalue3[4] <= syndcell_3:cell_3.port4
syndvalue4[0] <= syndcell_4:cell_4.port4
syndvalue4[1] <= syndcell_4:cell_4.port4
syndvalue4[2] <= syndcell_4:cell_4.port4
syndvalue4[3] <= syndcell_4:cell_4.port4
syndvalue4[4] <= syndcell_4:cell_4.port4
syndvalue5[0] <= syndcell_5:cell_5.port4
syndvalue5[1] <= syndcell_5:cell_5.port4
syndvalue5[2] <= syndcell_5:cell_5.port4
syndvalue5[3] <= syndcell_5:cell_5.port4
syndvalue5[4] <= syndcell_5:cell_5.port4
syndvalue6[0] <= syndcell_6:cell_6.port4
syndvalue6[1] <= syndcell_6:cell_6.port4
syndvalue6[2] <= syndcell_6:cell_6.port4
syndvalue6[3] <= syndcell_6:cell_6.port4
syndvalue6[4] <= syndcell_6:cell_6.port4
syndvalue7[0] <= syndcell_7:cell_7.port4
syndvalue7[1] <= syndcell_7:cell_7.port4
syndvalue7[2] <= syndcell_7:cell_7.port4
syndvalue7[3] <= syndcell_7:cell_7.port4
syndvalue7[4] <= syndcell_7:cell_7.port4
syndvalue8[0] <= syndcell_8:cell_8.port4
syndvalue8[1] <= syndcell_8:cell_8.port4
syndvalue8[2] <= syndcell_8:cell_8.port4
syndvalue8[3] <= syndcell_8:cell_8.port4
syndvalue8[4] <= syndcell_8:cell_8.port4
syndvalue9[0] <= syndcell_9:cell_9.port4
syndvalue9[1] <= syndcell_9:cell_9.port4
syndvalue9[2] <= syndcell_9:cell_9.port4
syndvalue9[3] <= syndcell_9:cell_9.port4
syndvalue9[4] <= syndcell_9:cell_9.port4
syndvalue10[0] <= syndcell_10:cell_10.port4
syndvalue10[1] <= syndcell_10:cell_10.port4
syndvalue10[2] <= syndcell_10:cell_10.port4
syndvalue10[3] <= syndcell_10:cell_10.port4
syndvalue10[4] <= syndcell_10:cell_10.port4
syndvalue11[0] <= syndcell_11:cell_11.port4
syndvalue11[1] <= syndcell_11:cell_11.port4
syndvalue11[2] <= syndcell_11:cell_11.port4
syndvalue11[3] <= syndcell_11:cell_11.port4
syndvalue11[4] <= syndcell_11:cell_11.port4
errdetect <= errdetect~0.DB_MAX_OUTPUT_PORT_TYPE
en_sccell => en_sccell~0.IN12
evalsynd => nxt_state.st2.DATAB
evalsynd => nxt_state.st1.IN1
holdsynd => holdsynd~0.IN12


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0
recword[4] => recword[4]~4.IN1
recword[3] => recword[3]~3.IN1
recword[2] => recword[2]~2.IN1
recword[1] => recword[1]~1.IN1
recword[0] => recword[0]~0.IN1
clock => clock~0.IN1
enable => enable~0.IN1
hold => hold~0.IN1
synvalue0[4] <= register5_wlh:register5bit.port1
synvalue0[3] <= register5_wlh:register5bit.port1
synvalue0[2] <= register5_wlh:register5bit.port1
synvalue0[1] <= register5_wlh:register5bit.port1
synvalue0[0] <= register5_wlh:register5bit.port1


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|register5_wlh:register5bit
datain[0] => out~9.DATAB
datain[1] => out~8.DATAB
datain[2] => out~7.DATAB
datain[3] => out~6.DATAB
datain[4] => out~5.DATAB
dataout[0] <= out[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= out[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= out[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= out[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= out[4].DB_MAX_OUTPUT_PORT_TYPE
load => out~5.OUTPUTSELECT
load => out~6.OUTPUTSELECT
load => out~7.OUTPUTSELECT
load => out~8.OUTPUTSELECT
load => out~9.OUTPUTSELECT
hold => out~0.OUTPUTSELECT
hold => out~1.OUTPUTSELECT
hold => out~2.OUTPUTSELECT
hold => out~3.OUTPUTSELECT
hold => out~4.OUTPUTSELECT
clock => out[3].CLK
clock => out[2].CLK
clock => out[1].CLK
clock => out[0].CLK
clock => out[4].CLK


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_0:cell_0|gfadder:adder
in1[4] => out~0.IN0
in1[3] => out~1.IN0
in1[2] => out~2.IN0
in1[1] => out~3.IN0
in1[0] => out~4.IN0
in2[4] => out~0.IN1
in2[3] => out~1.IN1
in2[2] => out~2.IN1
in2[1] => out~3.IN1
in2[0] => out~4.IN1
out[4] <= out~0.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out~2.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~3.DB_MAX_OUTPUT_PORT_TYPE
out[0] <= out~4.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1
recword[4] => recword[4]~4.IN1
recword[3] => recword[3]~3.IN1
recword[2] => recword[2]~2.IN1
recword[1] => recword[1]~1.IN1
recword[0] => recword[0]~0.IN1
clock => clock~0.IN1
enable => enable~0.IN1
hold => hold~0.IN1
synvalue1[4] <= register5_wlh:register5bit.port1
synvalue1[3] <= register5_wlh:register5bit.port1
synvalue1[2] <= register5_wlh:register5bit.port1
synvalue1[1] <= register5_wlh:register5bit.port1
synvalue1[0] <= register5_wlh:register5bit.port1


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|register5_wlh:register5bit
datain[0] => out~9.DATAB
datain[1] => out~8.DATAB
datain[2] => out~7.DATAB
datain[3] => out~6.DATAB
datain[4] => out~5.DATAB
dataout[0] <= out[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= out[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= out[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= out[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= out[4].DB_MAX_OUTPUT_PORT_TYPE
load => out~5.OUTPUTSELECT
load => out~6.OUTPUTSELECT
load => out~7.OUTPUTSELECT
load => out~8.OUTPUTSELECT
load => out~9.OUTPUTSELECT
hold => out~0.OUTPUTSELECT
hold => out~1.OUTPUTSELECT
hold => out~2.OUTPUTSELECT
hold => out~3.OUTPUTSELECT
hold => out~4.OUTPUTSELECT
clock => out[3].CLK
clock => out[2].CLK
clock => out[1].CLK
clock => out[0].CLK
clock => out[4].CLK


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_1:cell_1|gfadder:adder
in1[4] => out~0.IN0
in1[3] => out~1.IN0
in1[2] => out~2.IN0
in1[1] => out~3.IN0
in1[0] => out~4.IN0
in2[4] => out~0.IN1
in2[3] => out~1.IN1
in2[2] => out~2.IN1
in2[1] => out~3.IN1
in2[0] => out~4.IN1
out[4] <= out~0.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out~2.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~3.DB_MAX_OUTPUT_PORT_TYPE
out[0] <= out~4.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2
recword[4] => recword[4]~4.IN1
recword[3] => recword[3]~3.IN1
recword[2] => recword[2]~2.IN1
recword[1] => recword[1]~1.IN1
recword[0] => recword[0]~0.IN1
clock => clock~0.IN1
enable => enable~0.IN1
hold => hold~0.IN1
synvalue2[4] <= register5_wlh:register5bit.port1
synvalue2[3] <= register5_wlh:register5bit.port1
synvalue2[2] <= register5_wlh:register5bit.port1
synvalue2[1] <= register5_wlh:register5bit.port1
synvalue2[0] <= register5_wlh:register5bit.port1


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|register5_wlh:register5bit
datain[0] => out~9.DATAB
datain[1] => out~8.DATAB
datain[2] => out~7.DATAB
datain[3] => out~6.DATAB
datain[4] => out~5.DATAB
dataout[0] <= out[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= out[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= out[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= out[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= out[4].DB_MAX_OUTPUT_PORT_TYPE
load => out~5.OUTPUTSELECT
load => out~6.OUTPUTSELECT
load => out~7.OUTPUTSELECT
load => out~8.OUTPUTSELECT
load => out~9.OUTPUTSELECT
hold => out~0.OUTPUTSELECT
hold => out~1.OUTPUTSELECT
hold => out~2.OUTPUTSELECT
hold => out~3.OUTPUTSELECT
hold => out~4.OUTPUTSELECT
clock => out[3].CLK
clock => out[2].CLK
clock => out[1].CLK
clock => out[0].CLK
clock => out[4].CLK


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_2:cell_2|gfadder:adder
in1[4] => out~0.IN0
in1[3] => out~1.IN0
in1[2] => out~2.IN0
in1[1] => out~3.IN0
in1[0] => out~4.IN0
in2[4] => out~0.IN1
in2[3] => out~1.IN1
in2[2] => out~2.IN1
in2[1] => out~3.IN1
in2[0] => out~4.IN1
out[4] <= out~0.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out~2.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~3.DB_MAX_OUTPUT_PORT_TYPE
out[0] <= out~4.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3
recword[4] => recword[4]~4.IN1
recword[3] => recword[3]~3.IN1
recword[2] => recword[2]~2.IN1
recword[1] => recword[1]~1.IN1
recword[0] => recword[0]~0.IN1
clock => clock~0.IN1
enable => enable~0.IN1
hold => hold~0.IN1
synvalue3[4] <= register5_wlh:register5bit.port1
synvalue3[3] <= register5_wlh:register5bit.port1
synvalue3[2] <= register5_wlh:register5bit.port1
synvalue3[1] <= register5_wlh:register5bit.port1
synvalue3[0] <= register5_wlh:register5bit.port1


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|register5_wlh:register5bit
datain[0] => out~9.DATAB
datain[1] => out~8.DATAB
datain[2] => out~7.DATAB
datain[3] => out~6.DATAB
datain[4] => out~5.DATAB
dataout[0] <= out[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= out[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= out[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= out[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= out[4].DB_MAX_OUTPUT_PORT_TYPE
load => out~5.OUTPUTSELECT
load => out~6.OUTPUTSELECT
load => out~7.OUTPUTSELECT
load => out~8.OUTPUTSELECT
load => out~9.OUTPUTSELECT
hold => out~0.OUTPUTSELECT
hold => out~1.OUTPUTSELECT
hold => out~2.OUTPUTSELECT
hold => out~3.OUTPUTSELECT
hold => out~4.OUTPUTSELECT
clock => out[3].CLK
clock => out[2].CLK
clock => out[1].CLK
clock => out[0].CLK
clock => out[4].CLK


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_3:cell_3|gfadder:adder
in1[4] => out~0.IN0
in1[3] => out~1.IN0
in1[2] => out~2.IN0
in1[1] => out~3.IN0
in1[0] => out~4.IN0
in2[4] => out~0.IN1
in2[3] => out~1.IN1
in2[2] => out~2.IN1
in2[1] => out~3.IN1
in2[0] => out~4.IN1
out[4] <= out~0.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out~2.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~3.DB_MAX_OUTPUT_PORT_TYPE
out[0] <= out~4.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4
recword[4] => recword[4]~4.IN1
recword[3] => recword[3]~3.IN1
recword[2] => recword[2]~2.IN1
recword[1] => recword[1]~1.IN1
recword[0] => recword[0]~0.IN1
clock => clock~0.IN1
enable => enable~0.IN1
hold => hold~0.IN1
synvalue4[4] <= register5_wlh:register5bit.port1
synvalue4[3] <= register5_wlh:register5bit.port1
synvalue4[2] <= register5_wlh:register5bit.port1
synvalue4[1] <= register5_wlh:register5bit.port1
synvalue4[0] <= register5_wlh:register5bit.port1


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|register5_wlh:register5bit
datain[0] => out~9.DATAB
datain[1] => out~8.DATAB
datain[2] => out~7.DATAB
datain[3] => out~6.DATAB
datain[4] => out~5.DATAB
dataout[0] <= out[0].DB_MAX_OUTPUT_PORT_TYPE
dataout[1] <= out[1].DB_MAX_OUTPUT_PORT_TYPE
dataout[2] <= out[2].DB_MAX_OUTPUT_PORT_TYPE
dataout[3] <= out[3].DB_MAX_OUTPUT_PORT_TYPE
dataout[4] <= out[4].DB_MAX_OUTPUT_PORT_TYPE
load => out~5.OUTPUTSELECT
load => out~6.OUTPUTSELECT
load => out~7.OUTPUTSELECT
load => out~8.OUTPUTSELECT
load => out~9.OUTPUTSELECT
hold => out~0.OUTPUTSELECT
hold => out~1.OUTPUTSELECT
hold => out~2.OUTPUTSELECT
hold => out~3.OUTPUTSELECT
hold => out~4.OUTPUTSELECT
clock => out[3].CLK
clock => out[2].CLK
clock => out[1].CLK
clock => out[0].CLK
clock => out[4].CLK


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_4:cell_4|gfadder:adder
in1[4] => out~0.IN0
in1[3] => out~1.IN0
in1[2] => out~2.IN0
in1[1] => out~3.IN0
in1[0] => out~4.IN0
in2[4] => out~0.IN1
in2[3] => out~1.IN1
in2[2] => out~2.IN1
in2[1] => out~3.IN1
in2[0] => out~4.IN1
out[4] <= out~0.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out~1.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out~2.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out~3.DB_MAX_OUTPUT_PORT_TYPE
out[0] <= out~4.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5
recword[4] => recword[4]~4.IN1
recword[3] => recword[3]~3.IN1
recword[2] => recword[2]~2.IN1
recword[1] => recword[1]~1.IN1
recword[0] => recword[0]~0.IN1
clock => clock~0.IN1
enable => enable~0.IN1
hold => hold~0.IN1
synvalue5[4] <= register5_wlh:register5bit.port1
synvalue5[3] <= register5_wlh:register5bit.port1
synvalue5[2] <= register5_wlh:register5bit.port1
synvalue5[1] <= register5_wlh:register5bit.port1
synvalue5[0] <= register5_wlh:register5bit.port1


|rs|RSDecoder:inst1|rsdec:rsdec|SCblock:SCblock|syndcell_5:cell_5|register5_wlh:register5bit
datain[0] => out~9.DATAB
datain[1] => out~8.DATAB
datain[2] => out~7.DATAB