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RS编码的verilog源代码

|rs
bitout <= RSDecoder:inst1.decodeoutbit
clk => Clock:inst3.clk57
clk => RSDecoder:inst1.clk57_5
reset => RSDecoder:inst1.reset
reset => RSEncoder:inst.reset
reset => RSEncoder:inst.start
reset => nrz:inst2.reset
bitoutstart <= RSDecoder:inst1.decodeoutbitstart
errfound <= RSDecoder:inst1.errfound
fail <= RSDecoder:inst1.decode_fail
bitin <= nrz:inst2.out
bitinstart <= nrz:inst2.datastart
error <= error:inst6.errorout
adderror <= inst17.DB_MAX_OUTPUT_PORT_TYPE
be_adderror <= RSEncoder:inst.bitout


|rs|RSDecoder:inst1
clk19_5 => clk19_5~0.IN2
clk31_5 => clk31_5~0.IN2
clk57_5 => clk57_5~0.IN1
reset => reset~0.IN5
start => start~0.IN1
decodebitin => decodebitin~0.IN1
bitinstart => bitinstart~0.IN1
errfound <= rsdec:rsdec.port6
decode_fail <= rsdec:rsdec.port7
decodeoutbit <= Dec2Bit:Dec2Bit.port5
decodeoutbitstart <= Dec2Bit:Dec2Bit.port6
decodein[0] <= decodein[0]~4.DB_MAX_OUTPUT_PORT_TYPE
decodein[1] <= decodein[1]~3.DB_MAX_OUTPUT_PORT_TYPE
decodein[2] <= decodein[2]~2.DB_MAX_OUTPUT_PORT_TYPE
decodein[3] <= decodein[3]~1.DB_MAX_OUTPUT_PORT_TYPE
decodein[4] <= decodein[4]~0.DB_MAX_OUTPUT_PORT_TYPE
ram1out[0] <= ram1out[0]~4.DB_MAX_OUTPUT_PORT_TYPE
ram1out[1] <= ram1out[1]~3.DB_MAX_OUTPUT_PORT_TYPE
ram1out[2] <= ram1out[2]~2.DB_MAX_OUTPUT_PORT_TYPE
ram1out[3] <= ram1out[3]~1.DB_MAX_OUTPUT_PORT_TYPE
ram1out[4] <= ram1out[4]~0.DB_MAX_OUTPUT_PORT_TYPE
decodedataout[0] <= decodedataout[0]~4.DB_MAX_OUTPUT_PORT_TYPE
decodedataout[1] <= decodedataout[1]~3.DB_MAX_OUTPUT_PORT_TYPE
decodedataout[2] <= decodedataout[2]~2.DB_MAX_OUTPUT_PORT_TYPE
decodedataout[3] <= decodedataout[3]~1.DB_MAX_OUTPUT_PORT_TYPE
decodedataout[4] <= decodedataout[4]~0.DB_MAX_OUTPUT_PORT_TYPE
decodeout[0] <= decodeout[0]~4.DB_MAX_OUTPUT_PORT_TYPE
decodeout[1] <= decodeout[1]~3.DB_MAX_OUTPUT_PORT_TYPE
decodeout[2] <= decodeout[2]~2.DB_MAX_OUTPUT_PORT_TYPE
decodeout[3] <= decodeout[3]~1.DB_MAX_OUTPUT_PORT_TYPE
decodeout[4] <= decodeout[4]~0.DB_MAX_OUTPUT_PORT_TYPE
decodeinstart <= decodeinstart~0.DB_MAX_OUTPUT_PORT_TYPE
ram1outstart <= ram1outstart~0.DB_MAX_OUTPUT_PORT_TYPE
dataoutstart <= dataoutstart~0.DB_MAX_OUTPUT_PORT_TYPE
decodeoutstart <= decodeoutstart~0.DB_MAX_OUTPUT_PORT_TYPE
wraddress1[0] <= wraddress1[0]~4.DB_MAX_OUTPUT_PORT_TYPE
wraddress1[1] <= wraddress1[1]~3.DB_MAX_OUTPUT_PORT_TYPE
wraddress1[2] <= wraddress1[2]~2.DB_MAX_OUTPUT_PORT_TYPE
wraddress1[3] <= wraddress1[3]~1.DB_MAX_OUTPUT_PORT_TYPE
wraddress1[4] <= wraddress1[4]~0.DB_MAX_OUTPUT_PORT_TYPE
rdaddress1[0] <= rdaddress1[0]~4.DB_MAX_OUTPUT_PORT_TYPE
rdaddress1[1] <= rdaddress1[1]~3.DB_MAX_OUTPUT_PORT_TYPE
rdaddress1[2] <= rdaddress1[2]~2.DB_MAX_OUTPUT_PORT_TYPE
rdaddress1[3] <= rdaddress1[3]~1.DB_MAX_OUTPUT_PORT_TYPE
rdaddress1[4] <= rdaddress1[4]~0.DB_MAX_OUTPUT_PORT_TYPE
wraddress2[0] <= wraddress2[0]~4.DB_MAX_OUTPUT_PORT_TYPE
wraddress2[1] <= wraddress2[1]~3.DB_MAX_OUTPUT_PORT_TYPE
wraddress2[2] <= wraddress2[2]~2.DB_MAX_OUTPUT_PORT_TYPE
wraddress2[3] <= wraddress2[3]~1.DB_MAX_OUTPUT_PORT_TYPE
wraddress2[4] <= wraddress2[4]~0.DB_MAX_OUTPUT_PORT_TYPE
rdaddress2[0] <= rdaddress2[0]~4.DB_MAX_OUTPUT_PORT_TYPE
rdaddress2[1] <= rdaddress2[1]~3.DB_MAX_OUTPUT_PORT_TYPE
rdaddress2[2] <= rdaddress2[2]~2.DB_MAX_OUTPUT_PORT_TYPE
rdaddress2[3] <= rdaddress2[3]~1.DB_MAX_OUTPUT_PORT_TYPE
rdaddress2[4] <= rdaddress2[4]~0.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|divide5:dividea
clk_in => counter[1].CLK
clk_in => counter[0].CLK
clk_in => clk_temp1.CLK
clk_in => counter[2].CLK
clk_in => clk_temp2.CLK
rst => clk_temp2~0.OUTPUTSELECT
rst => counter~6.OUTPUTSELECT
rst => counter~7.OUTPUTSELECT
rst => counter~8.OUTPUTSELECT
rst => clk_temp1~2.OUTPUTSELECT
clk_out <= clk_out~0.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|divide5:divideb
clk_in => counter[1].CLK
clk_in => counter[0].CLK
clk_in => clk_temp1.CLK
clk_in => counter[2].CLK
clk_in => clk_temp2.CLK
rst => clk_temp2~0.OUTPUTSELECT
rst => counter~6.OUTPUTSELECT
rst => counter~7.OUTPUTSELECT
rst => counter~8.OUTPUTSELECT
rst => clk_temp1~2.OUTPUTSELECT
clk_out <= clk_out~0.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|divide5:dividec
clk_in => counter[1].CLK
clk_in => counter[0].CLK
clk_in => clk_temp1.CLK
clk_in => counter[2].CLK
clk_in => clk_temp2.CLK
rst => clk_temp2~0.OUTPUTSELECT
rst => counter~6.OUTPUTSELECT
rst => counter~7.OUTPUTSELECT
rst => counter~8.OUTPUTSELECT
rst => clk_temp1~2.OUTPUTSELECT
clk_out <= clk_out~0.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|Bit2Dec:Bit2Dec
reset => cnt[1].ACLR
reset => cnt[0].ACLR
reset => out[4]~reg0.ACLR
reset => out[3]~reg0.ACLR
reset => out[2]~reg0.ACLR
reset => out[1]~reg0.ACLR
reset => out[0]~reg0.ACLR
reset => outstart~reg0.ACLR
reset => enable.ACLR
reset => cnt[2].ACLR
start => enable.CLK
clkin => cnt[1].CLK
clkin => cnt[0].CLK
clkin => out[4]~reg0.CLK
clkin => out[3]~reg0.CLK
clkin => out[2]~reg0.CLK
clkin => out[1]~reg0.CLK
clkin => out[0]~reg0.CLK
clkin => outstart~reg0.CLK
clkin => c2.CLK
clkin => c3.CLK
clkin => c4.CLK
clkin => c5.CLK
clkin => c1.CLK
clkin => cnt[2].CLK
in => c1.DATAIN
clkout => ~NO_FANOUT~
out[0] <= out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
outstart <= outstart~reg0.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|before_decode:before_decode
clk1 => wraddress[3]~reg0.CLK
clk1 => wraddress[2]~reg0.CLK
clk1 => wraddress[1]~reg0.CLK
clk1 => wraddress[0]~reg0.CLK
clk1 => wrclocken~reg0.CLK
clk1 => wren~reg0.CLK
clk1 => temp[4].CLK
clk1 => temp[3].CLK
clk1 => temp[2].CLK
clk1 => temp[1].CLK
clk1 => temp[0].CLK
clk1 => wraddress[4]~reg0.CLK
clk2 => rdaddress[3]~reg0.CLK
clk2 => rdaddress[2]~reg0.CLK
clk2 => rdaddress[1]~reg0.CLK
clk2 => rdaddress[0]~reg0.CLK
clk2 => rdclocken~reg0.CLK
clk2 => wordstart~reg0.CLK
clk2 => temp1[5].CLK
clk2 => temp1[4].CLK
clk2 => temp1[3].CLK
clk2 => temp1[2].CLK
clk2 => temp1[1].CLK
clk2 => temp1[0].CLK
clk2 => rdaddress[4]~reg0.CLK
reset => rdaddress[3]~reg0.ACLR
reset => rdaddress[2]~reg0.ACLR
reset => rdaddress[1]~reg0.ACLR
reset => rdaddress[0]~reg0.ACLR
reset => rdclocken~reg0.ACLR
reset => wordstart~reg0.ACLR
reset => temp1[5].ACLR
reset => temp1[4].ACLR
reset => temp1[3].ACLR
reset => temp1[2].ACLR
reset => temp1[1].ACLR
reset => temp1[0].ACLR
reset => wraddress[3]~reg0.ACLR
reset => rdaddress[4]~reg0.ACLR
reset => wraddress[2]~reg0.ACLR
reset => wraddress[1]~reg0.ACLR
reset => wraddress[0]~reg0.ACLR
reset => wrclocken~reg0.ACLR
reset => wren~reg0.ACLR
reset => temp[4].ACLR
reset => temp[3].ACLR
reset => temp[2].ACLR
reset => temp[1].ACLR
reset => temp[0].PRESET
reset => wraddress[4]~reg0.ACLR
reset => enable.ACLR
start => ~NO_FANOUT~
rdaddress[0] <= rdaddress[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rdaddress[1] <= rdaddress[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rdaddress[2] <= rdaddress[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rdaddress[3] <= rdaddress[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rdaddress[4] <= rdaddress[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rdclocken <= rdclocken~reg0.DB_MAX_OUTPUT_PORT_TYPE
wraddress[0] <= wraddress[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wraddress[1] <= wraddress[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wraddress[2] <= wraddress[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wraddress[3] <= wraddress[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wraddress[4] <= wraddress[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wrclocken <= wrclocken~reg0.DB_MAX_OUTPUT_PORT_TYPE
wren <= wren~reg0.DB_MAX_OUTPUT_PORT_TYPE
inwordstart => enable.CLK
wordstart <= wordstart~reg0.DB_MAX_OUTPUT_PORT_TYPE


|rs|RSDecoder:inst1|lpm_ram_dp0:ram1
data[0] => data[0]~4.IN1
data[1] => data[1]~3.IN1
data[2] => data[2]~2.IN1
data[3] => data[3]~1.IN1
data[4] => data[4]~0.IN1
rdaddress[0] => rdaddress[0]~4.IN1
rdaddress[1] => rdaddress[1]~3.IN1
rdaddress[2] => rdaddress[2]~2.IN1
rdaddress[3] => rdaddress[3]~1.IN1
rdaddress[4] => rdaddress[4]~0.IN1
rdclock => rdclock~0.IN1
rdclocken => rdclocken~0.IN1
wraddress[0] => wraddress[0]~4.IN1
wraddress[1] => wraddress[1]~3.IN1
wraddress[2] => wraddress[2]~2.IN1
wraddress[3] => wraddress[3]~1.IN1
wraddress[4] => wraddress[4]~0.IN1
wrclock => wrclock~0.IN1
wrclocken => wrclocken~0.IN1
wren => wren~0.IN1
q[0] <= altsyncram:altsyncram_component.q_b
q[1] <= altsyncram:altsyncram_component.q_b
q[2] <= altsyncram:altsyncram_component.q_b
q[3] <= altsyncram:altsyncram_component.q_b
q[4] <= altsyncram:altsyncram_component.q_b


|rs|RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component
wren_a => altsyncram_lva1:auto_generated.wren_a
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_lva1:auto_generated.data_a[0]
data_a[1] => altsyncram_lva1:auto_generated.data_a[1]
data_a[2] => altsyncram_lva1:auto_generated.data_a[2]
data_a[3] => altsyncram_lva1:auto_generated.data_a[3]
data_a[4] => altsyncram_lva1:auto_generated.data_a[4]
data_b[0] => ~NO_FANOUT~
data_b[1] => ~NO_FANOUT~
data_b[2] => ~NO_FANOUT~
data_b[3] => ~NO_FANOUT~
data_b[4] => ~NO_FANOUT~
address_a[0] => altsyncram_lva1:auto_generated.address_a[0]
address_a[1] => altsyncram_lva1:auto_generated.address_a[1]
address_a[2] => altsyncram_lva1:auto_generated.address_a[2]
address_a[3] => altsyncram_lva1:auto_generated.address_a[3]
address_a[4] => altsyncram_lva1:auto_generated.address_a[4]
address_b[0] => altsyncram_lva1:auto_generated.address_b[0]
address_b[1] => altsyncram_lva1:auto_generated.address_b[1]
address_b[2] => altsyncram_lva1:auto_generated.address_b[2]
address_b[3] => altsyncram_lva1:auto_generated.address_b[3]
address_b[4] => altsyncram_lva1:auto_generated.address_b[4]
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_lva1:auto_generated.clock0
clock1 => altsyncram_lva1:auto_generated.clock1
clocken0 => altsyncram_lva1:auto_generated.clocken0
clocken1 => altsyncram_lva1:auto_generated.clocken1
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= <GND>
q_a[1] <= <GND>
q_a[2] <= <GND>
q_a[3] <= <GND>
q_a[4] <= <GND>
q_b[0] <= altsyncram_lva1:auto_generated.q_b[0]
q_b[1] <= altsyncram_lva1:auto_generated.q_b[1]
q_b[2] <= altsyncram_lva1:auto_generated.q_b[2]
q_b[3] <= altsyncram_lva1:auto_generated.q_b[3]
q_b[4] <= altsyncram_lva1:auto_generated.q_b[4]


|rs|RSDecoder:inst1|lpm_ram_dp0:ram1|altsyncram:altsyncram_component|altsyncram_lva1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock1 => ram_block1a0.CLK1
clock1 => ram_block1a1.CLK1
clock1 => ram_block1a2.CLK1
clock1 => ram_block1a3.CLK1
clock1 => ram_block1a4.CLK1
clocken0 => ram_block1a0.ENA0
clocken0 => ram_block1a1.ENA0
clocken0 => ram_block1a2.ENA0
clocken0 => ram_block1a3.ENA0
clocken0 => ram_block1a4.ENA0
clocken1 => ram_block1a0.ENA1
clocken1 => ram_block1a1.ENA1
clocken1 => ram_block1a2.ENA1
clocken1 => ram_block1a3.ENA1
clocken1 => ram_block1a4.ENA1
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE


|rs|RSDecoder:inst1|rsdec:rsdec
recword[0] => recword[0]~4.IN2
recword[1] => recword[1]~3.IN2
recword[2] => recword[2]~2.IN2
recword[3] => recword[3]~1.IN2
recword[4] => recword[4]~0.IN2
start => start~0.IN1
clock1 => clock1~0.IN5
clock2 => clock2~0.IN5
reset => reset~0.IN4
ready <= MainControl:controller.port15
errfound <= MainControl:controller.port13
decode_fail <= MainControl:controller.port14
dataoutstart <= MainControl:controller.port16
dataoutend <= MainControl:controller.port17
corr_recword[0] <= gfadder:adder.port2
corr_recword[1] <= gfadder:adder.port2
corr_recword[2] <= gfadder:adder.port2
corr_recword[3] <= gfadder:adder.port2
corr_recword[4] <= gfadder:adder.port2