top.map.qmsg

RS编码的verilog源代码

{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 1 fifo_register.v(25) " "Warning (10271): Verilog HDL Case Statement warning at fifo_register.v(25): size of case item expression (32) exceeds the size of the case expression (1)" {  } { { "fifo_register.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/fifo_register.v" 25 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 1 fifo_register.v(26) " "Warning (10271): Verilog HDL Case Statement warning at fifo_register.v(26): size of case item expression (32) exceeds the size of the case expression (1)" {  } { { "fifo_register.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/fifo_register.v" 26 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fifo_decode RSDecoder:inst1\|fifo_decode:fifo_decode " "Info: Elaborating entity \"fifo_decode\" for hierarchy \"RSDecoder:inst1\|fifo_decode:fifo_decode\"" {  } { { "RSDecoder.v" "fifo_decode" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RSDecoder.v" 42 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 RAM_fifo_all.v(133) " "Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(133): truncated value with size 32 to match size of target (6)" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 133 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 RAM_fifo_all.v(141) " "Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(141): truncated value with size 32 to match size of target (6)" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 141 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 5 RAM_fifo_all.v(142) " "Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(142): truncated value with size 6 to match size of target (5)" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 142 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "isword1 RAM_fifo_all.v(103) " "Warning (10240): Verilog HDL Always Construct warning at RAM_fifo_all.v(103): variable \"isword1\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"isword1\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 103 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 RAM_fifo_all.v(178) " "Warning (10230): Verilog HDL assignment warning at RAM_fifo_all.v(178): truncated value with size 32 to match size of target (5)" {  } { { "RAM_fifo_all.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RAM_fifo_all.v" 178 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Dec2Bit RSDecoder:inst1\|Dec2Bit:Dec2Bit " "Info: Elaborating entity \"Dec2Bit\" for hierarchy \"RSDecoder:inst1\|Dec2Bit:Dec2Bit\"" {  } { { "RSDecoder.v" "Dec2Bit" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/RSDecoder.v" 48 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "clkin serial_paralled_conversion.v(2) " "Info (10035): Verilog HDL or VHDL information at serial_paralled_conversion.v(2): object \"clkin\" declared but not used" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 2 0 0 } }  } 0 10035 "Verilog HDL or VHDL information at %2!s!: object \"%1!s!\" declared but not used" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 serial_paralled_conversion.v(35) " "Warning (10230): Verilog HDL assignment warning at serial_paralled_conversion.v(35): truncated value with size 32 to match size of target (3)" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 35 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 serial_paralled_conversion.v(37) " "Warning (10271): Verilog HDL Case Statement warning at serial_paralled_conversion.v(37): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 37 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 serial_paralled_conversion.v(38) " "Warning (10271): Verilog HDL Case Statement warning at serial_paralled_conversion.v(38): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 38 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 serial_paralled_conversion.v(39) " "Warning (10271): Verilog HDL Case Statement warning at serial_paralled_conversion.v(39): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 39 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 serial_paralled_conversion.v(40) " "Warning (10271): Verilog HDL Case Statement warning at serial_paralled_conversion.v(40): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 40 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_CASE_ITEM_EXPR_TOO_LARGE" "32 3 serial_paralled_conversion.v(41) " "Warning (10271): Verilog HDL Case Statement warning at serial_paralled_conversion.v(41): size of case item expression (32) exceeds the size of the case expression (3)" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 41 0 0 } }  } 0 10271 "Verilog HDL Case Statement warning at %3!s!: size of case item expression (%1!d!) exceeds the size of the case expression (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "serial_paralled_conversion.v(36) " "Warning (10270): Verilog HDL statement warning at serial_paralled_conversion.v(36): incomplete Case Statement has no default case item" {  } { { "serial_paralled_conversion.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/serial_paralled_conversion.v" 36 0 0 } }  } 0 10270 "Verilog HDL statement warning at %1!s!: incomplete Case Statement has no default case item" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Clock Clock:inst3 " "Info: Elaborating entity \"Clock\" for hierarchy \"Clock:inst3\"" {  } { { "rs.bdf" "inst3" { Schematic "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/rs.bdf" { { 88 104 200 184 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll Clock:inst3\|pll:p31_57 " "Info: Elaborating entity \"pll\" for hierarchy \"Clock:inst3\|pll:p31_57\"" {  } { { "Clock.v" "p31_57" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/Clock.v" 7 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../altera/quartus51/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../altera/quartus51/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altpll.tdf" 363 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll Clock:inst3\|pll:p31_57\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"Clock:inst3\|pll:p31_57\|altpll:altpll_component\"" {  } { { "pll.v" "altpll_component" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/pll.v" 56 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "divide3 Clock:inst3\|divide3:divideb " "Info: Elaborating entity \"divide3\" for hierarchy \"Clock:inst3\|divide3:divideb\"" {  } { { "Clock.v" "divideb" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/Clock.v" 8 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 frequency divider.v(57) " "Warning (10230): Verilog HDL assignment warning at frequency divider.v(57): truncated value with size 32 to match size of target (3)" {  } { { "frequency divider.v" "" { Text "D:/6.11开始/RS_19_31_EP1C6Q240_TEST1/frequency divider.v" 57 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RSEncoder RSEncoder:inst " "Info: Elaborating entity \"RSEncoder\" for hierarchy \"RSEncoder:inst\"" {  } { { "rs.bdf" "inst" { Schematic "